ts32mls64v6d Transcend Information. Inc., ts32mls64v6d Datasheet - Page 10

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ts32mls64v6d

Manufacturer Part Number
ts32mls64v6d
Description
168pin Pc133 Unbuffered Dimm 256mb With 16mx8 Cl3 Placement
Manufacturer
Transcend Information. Inc.
Datasheet
Transcend Information Inc.
T
T
Byte No.
T
Serial Presence Detect Specification
36-61 Superset Information
64-71 Manufacturers JEDEC ID Code per JEP-108E
73-90 Manufacturers Part Number
S
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
62
63
72
S
S
0
1
2
3
4
5
6
7
8
9
3
3
3
# of Bytes Written into Serial Memory
Total # of Bytes of S.P.D Memory
Fundamental Memory Type
# of Row Addresses on this Assembly
# of Column Addresses on this Assembly
# of Module Rows on this Assembly
Data Width of this Assembly
Data Width of this Assembly
Voltage Interface Standard of this Assembly
SDRAM Cycle Time @CAS latency of 3
SDRAM Access Time from Clock @CAS latency of 3
DIMM configuration type (non-parity, ECC)
Refresh Rate Type
Primary SDRAM Width
Error Checking SDRAM Width
Min Clock Delay for Back to Back Random Address
SDRAM Device Attributes: Burst Lengths Supported
SDRAM Device Attributes: # of banks on SDRAM device
SDRAM Device Attributes: CAS Latency
SDRAM Device Attributes: CS Latency
SDRAM Device Attributes: Write Latency
SDRAM Module Attributes
SDRAM Device Attributes: General
SDRAM Cycle Time @CAS Latency of 2
SDRAM Access Time from Clock @CAS Latency of 2
SDRAM Cycle Time @CAS Latency of 1
SDRAM Access Time from Clock @CAS Latency of 1
Minimum Row Precharge Time (=t RP)
Minimum Row Active to Row Activate (=t RRD)
Minimum RAS to CAS Delay (=t RCD)
Minimum Activate Precharge Time (=t RAS)
Module Row Density
Command and Address Signal input Setup Time
Command and Address Signal input Hold Time
Data Signal Setup Time
Data Signal Hold Time
SPD Data Revision Code
Checksum for Bytes 0-62
Manufacturing Location
2
2
2
M
M
M
L
L
L
S
S
S
6
6
6
4
4
4
Function Described
V
V
V
6
6
6
D
D
D
Serial Presence Detect
10
Non-buffered, non-registered
Burst Read Signal bit Write
+/- 10% voltage tolerance,
& redundant addressing
Standard Specification
15.625us/Self Refresh
1,2,4,8 & Full page
precharge all, auto
168PIN PC133 Unbuffered DIMM
TS32MLS64V6D
2 rows of 128MB
tCCD=1CLK
LVTTL3.3V
Transcend
precharge
128bytes
256bytes
JEDEC2
SDRAM
0 clock
0 clock
2 rows
4 bank
64bits
7.5ns
5.4ns
1.5ns
0.8ns
1.5ns
0.8ns
None
None
10ns
20ns
15ns
20ns
45ns
6ns
2,3
X8
12
10
T
-
-
-
-
-
256MB With 16Mx8 CL3
54 53 33 32 4D 4C
53 36 34 56 36 44
Vendor Part
7F, 4F
2D
0C
0A
0E
A0
0F
A0
80
08
04
02
40
00
01
75
54
00
80
08
00
01
8F
04
06
01
01
00
60
00
00
14
14
20
15
08
15
08
00
02
54

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