mc45488fn Lansdale Semiconductor, Inc., mc45488fn Datasheet - Page 3

• Manufacturer Part Number: mc45488fn
• Description: Dual Data Link Controller
• Manufacturer: Lansdale Semiconductor, Inc.

ML145488
DDLC OVERVIEW
high–performance two–channel protocol controller with an
on–chip direct memory access controller (DMAC). Each channel
has a full–duplex transceiver with independent protocol con-
trollers to handle the bit–level tasks of HDLC–type bit–oriented
protocols, including LAPB and LAPD. Each channel also has
dedicated DMA controllers for transmit and receive. A transparent
mode is provided which bypasses the protocol circuitry so that
serial data may be directly transferred between the host proces-
sor’s memory and the serial interface. The DDLC’s microproces-
sor interface is configurable to 68000 or 80186 systems and may
be used in 8–bit or16–bit bus modes. The DDLC’s master clock
can be obtained from microprocessor clocks up to 20.5 MHz.
and above T1 or E1 primary rate speeds in three modes: IDL,
Timeslot, and Modem. In the IDL (Interchip Digital Link) mode
for ISDN applications, the IDL bus is supported. When in the
IDL D channel mode, the DREQ and DGRNT access control
lines to the ISDN D channel, through the MC145474 S/T trans-
ceiver, are enabled. The timeslot mode is used to connect the
DDLC to PBX–type PCM high-way backplanes. Both long–frame
and short–frame timing are supported as well as synchronous
transmit and receive. In the modem mode, each channel has its
own separate transmit and receive clock inputs along with modem
control lines (RTS, CTS, and CD). The two channels are indepen-
dent and may be in different interface modes.
tion to other devices in a system. The SCP is compatible with
Motorola’s Serial Peripheral Interface (SPI) and National
Semiconductor’s MICROWIRE
used for general purpose, low resolution timing of HDLC–type
protocols. One of the timers may be configured as a watchdog
timer to reset the entire system in the event of a hardware or soft-
ware failure.
designs, and the DDLC was designed to use the minimum power
possible while maintaining maximum functionality. The DDLC
keeps power consumption to a minimum with an automatic
power–down feature that turns off sections of circuitry that are not
being used. Only those circuits that are actually used (e.g., when
the CS pin is activated for a register read/write or when the DMA
controller performs a bus transaction) enter the normal power
state for the duration of the access and for any time required for
internal processing.
test modes are available. The loopbacks are controlled by the host
for on–line maintenance. The test modes are activated by bits in
the master control register and provide access to the internal state
machines.
HDLC PROTOCOL OVERVIEW
LAPB (Link Access Protocol–Balanced) and LAPD (Link Access
Protocol for the D channel), are bit–oriented synchronous proto-
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The ML145488 Dual Data Link Controller (DDLC) is a
Each channel has a serial data interface which operates up to
A serial control port (SCP) is provided to pass control informa-
Power consumption is an important aspect of ISDN terminal
Two internal loopback functions and special chip and system
HDLC (High–Level Data Link Control) and its descendants,
GENERAL DESCRIPTION
™
Plus. Two internal timers may be
www.lansdale.com
cols which are widely used in data communications systems.
LAPB and LAPD share the basic format of HDLC but differ in
minor aspects (see Figure 1).
format called a frame or packet. All frames start with an opening
flag and end with a closing flag. Between the flags, a frame con-
tains an address field, control field, information field, and a cyclic
redundancy check field (CRC).
Flag
the frame boundary and a reference for the position of each field
of the frame.
Address Field
address field. The address field is used to distinguish between the
various devices in a network. The DDLC has address recognition
circuitry included, which relieves the host from this task.
Control Field
field. Commands and responses between the devices in a network
are exchanged in this field.
Information Field
The information field contains the data to be transferred and may
be a null field.
Cycle Redundancy Check Field
Redundancy Check (CRC) field. This field detects bit errors in
the address, control, and information fields. Checking is with the
standard CCITT polynominal x 16 x 12 x 5 + 1 for both the transmit-
ter and receiver. The transmitter calculates the CRC on all bits of
the frame (except for the flags) and transmits the complement of
the resulting remainder as the CRC field. The receiver performs
the similar computation on all bits (except for the flags) and com-
pares the result to F0B8.
Zero Insertion and Deletion
frame to be transparent, is automatically performed by the DDLC.
A binary 0 is inserted by the transmitter after any succession of
five 1s within a frame (between flags). This eliminates the possi-
bility of data imitating a flag character. The receiver deletes all 0s
that were inserted by the transmitter to regenerate the original data.
In the packet mode, the DDLC transmits and receives data in a
The flag is the unique binary pattern (01111110). It provides
The 8 or 16 bits following the opening flag comprise the
The 8 or 16 bits following the address field are the control
This field follows the control field and precedes the CRC field.
The 16 bits preceding the closing flag are the Cyclic
Zero insertion and deletion, which allows the content of the
FLAG
8 BITS
ADDRESS CONTROL
8 OR 16
BITS
Figure 1. HDLC Frame Format
8 OR 16
BITS
LANSDALE Semiconductor, Inc.
INFORMATION
n BITS
16 BITS
CRC
FLAG
8 BITS
Issue A