mc45488fn Lansdale Semiconductor, Inc., mc45488fn Datasheet
mc45488fn
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mc45488fn Summary of contents
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... ML145488 Dual Data Link Controller 68 1 CROSS REFERENCE/ORDERING INFORMATION PACKAGE PLCC Note: Lansdale lead free (Pb) product becomes available, will be identified by a part number prefix change from ML to MLE. www.lansdale.com PLCC 68 = -4P PLCC PACKAGE CASE 779 MOTOROLA LANSDALE MC45488FN ML145488-4P Issue A ...
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... PLCC 52 (TOP VIEW www.lansdale.com LANSDALE Semiconductor, Inc. TIMERS STATUS/ CONTROL REGISTERS 16–BIT BUS DMA CONTROLLER 26 D15 25 D14 24 D13 23 D12 22 D11 D10 19 D9 ...
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... A binary 0 is inserted by the transmitter after any succession of five 1s within a frame (between flags). This eliminates the possi- bility of data imitating a flag character. The receiver deletes all 0s that were inserted by the transmitter to regenerate the original data. www.lansdale.com LANSDALE Semiconductor, Inc. n BITS 16 BITS 8 BITS INFORMATION ...
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... D channel operation. In this mode, Request–To–Send (RTS) is directly controlled by theTransmit Enable (TE) bit. When TE is high, the RTS pin is asserted (low). During inter–frame periods, either flags or www.lansdale.com LANSDALE Semiconductor, Inc. ABORT ABORT OR ABORT NO CTS SENT ...
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... No interrupt is generated. State Diagram Figure 4 shows the state diagram of the receiver. SERIAL CONTROL PORT Tx BIT Tx HANDLER FIFO Rx Rx BIT FIFO HANDLER INTERRUPTS Figure 3. DDLC Block Diagram (One Transceiver Shown) www.lansdale.com LANSDALE Semiconductor, Inc. TIMERS MPU BUS DMA MPU CONTROLLER INTERFACE Issue A ...
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... The DDLC services one DMA request per bus arbitration cycle. The DDLC does not perform burst DMAs, so other devices can have access to the microprocessor bus. This type of operation improves system performance and guarantees that the DDLC is well behaved. www.lansdale.com LANSDALE Semiconductor, Inc. Issue A ...
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... The host can read from or write to the registers in the DDLC. This mode is entered when the CS pin is activated. Internal address decoding circuitry is selected and the desired reg- ister is connected to the internal bus for access by the host. www.lansdale.com LANSDALE Semiconductor, Inc. NOTE Issue A ...
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... BUS BG BUS GRANTED NORMAL BUS TERMINATION CYCLE NO DTACK BUS ERROR DISABLE CHANNEL Figure 5. Transmit DMA State Diagram AB00 BUFFER 1 AD00 BUFFER 2 Figure 6. Alternate Receive Buffer Operation www.lansdale.com LANSDALE Semiconductor, Inc. BUFFER EMPTY CLOSE BUFFER B300 BUFFER 3 B500 BUFFER 4 SYSTEM MEMORY Issue A ...
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... BUS GRANTED BUS NORMAL CYCLE TERMINATION BUS ERROR DISABLE CHANNEL Figure 7. Receive DMA State Diagram ÷ 1024 PRESCALE SELECT Figure 8. Timer Clock Selection www.lansdale.com LANSDALE Semiconductor, Inc. NORMAL EOF CLOSE BUFFER DTACK TIMER 0 UP–TIMER MODE DOWN–WATCHDOG MODE ÷ 16 ...
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... DDLC data book. The address for each register is the hexadecimal offset from the base address of the chip select. The registers may be accessed as 8–bit registers or 16–bit registers. Table map of the registers and their principal function. www.lansdale.com LANSDALE Semiconductor, Inc. Issue A ...
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... CHANNEL 1 Tx FRAME LENGTH CHANNEL 1 Tx BASE ADDRESS CHANNEL 1 Tx BYTE COUNT CHANNEL 1 Rx BUFFER LENGTH CHANNEL 1 Rx BUFFER A BASE ADDRESS CHANNEL 1 Rx BUFFER A BYTE COUNT CHANNEL 1 Rx BUFFER B BASE ADDRESS CHANNEL 1 Rx BUFFER B BYTE COUNT www.lansdale.com LANSDALE Semiconductor, Inc. Issue A ...
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... Lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the cus- tomer’s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc. Page ...