mb91101 Fujitsu Microelectronics, Inc., mb91101 Datasheet - Page 7

• Manufacturer Part Number: mb91101
• Description: 32-bit Risc Microcontroller Cmos
• Manufacturer: Fujitsu Microelectronics, Inc.

*1: FPT-100P-M05
*2: FPT-100P-M06
LQFP*
100
11
10
96
97
98
99
9
8
7
6
5
Pin no.
1
QFP*
100
14
13
12
11
10
99
9
8
1
2
3
2
Pin name
EOP1
RAS0
CS0H
RAS1
EOP2
CS0L
DW0
CS0
CS1
CS2
CS3
CS4
CS5
CLK
PA1
PA2
PA3
PA4
PA5
PA6
PB0
PB1
PB2
PB3
PB4
Circuit
type
L
F
F
F
F
F
F
F
F
F
F
F
Chip select 0 output (“L” active)
Chip select 1 output (“L” active)
Can be configured as a port when CS1 is not used.
Chip select 2 output (“L” active)
Can be configured as a port when CS2 is not used.
Chip select 3 output (“L” active)
Can be configured as a port when CS3 and EOP1 are not used.
EOP output pin for DMAC (ch. 1)
This function is available when EOP output for DMAC is en-
abled.
Chip select 4 output (“L” active)
Can be configured as a port when CS4 is not used.
Chip select 5 output (“L” active)
Can be configured as a port when CS5 is not used.
System clock output
Outputs clock signal of external bus operating frequency.
Can be configured as a port when CLK is not used.
RAS output for DRAM bank 0
Refer to the DRAM interface for details.
Can be configured as a port when RAS0 is not used.
CASL output for DRAM bank 0
Refer to the DRAM interface for details.
Can be configured as a port when CS0L is not used.
CASH output for DRAM bank 0
Refer to the DRAM interface for details.
Can be configured as a port when CS0H is not used.
WE output for DRAM bank 0 (“L” active)
Refer to the DRAM interface for details.
Can be configured as a port when DW0 is not used.
RAS output for DRAM bank 1
Refer to the DRAM interface for details.
Can be configured as a port when RAS1 and EOP2 are not
used.
DMAC EOP output (ch. 2)
This function is available when DMAC EOP output is enabled.
MB91101/MB91101A
Description
(Continued)
7