mb91101 Fujitsu Microelectronics, Inc., mb91101 Datasheet
mb91101
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mb91101 Summary of contents
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... CPU processing for embedded controller applications. To support the vast memory space accessed by the 32-bit CPU, the MB91101 and MB91101A normally operate in the external bus access mode and executes instructions on the internal 1 Kbyte cache memory and 2 Kbytes RAM for enhanced performance. ...
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... MB91101/MB91101A • Register interlock functions, efficient assembly language coding • Branch instructions with delay slots: Reduced overhead time in branch executions • Internal multiplier/supported at instruction level Signed 32-bit multiplication: 5 cycles Signed 16-bit multiplication: 3 cycles • Interrupt (push PC and PS): 6 cycles, 16 priority levels External bus interface • ...
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... However, operating frequency for peripherals is less than 25 MHz. • Packages: LQFP-100 and QFP-100 • CMOS technology (0.35 m) • Power supply voltage 5 V: CPU power supply 5.0 V 10% (internal regulator) A/D power supply 2 3 CPU power supply 2 3.6 V (without internal regulator) A/D power supply 2 3.6 V MB91101/MB91101A 4 (INT0 to INT3) 3 ...
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... MB91101/MB91101A PIN ASSIGNMENT CS1L/PB5/DREQ2 1 CS1H/PB6/DACK2 2 DW1/PB7 CLK/PA6 5 6 CS5/PA5 7 CS4/PA4 CS3/PA3/EOP1 8 9 CS2/PA2 10 CS1/PA1 11 CS0 12 NMI HST 13 14 RST MD0 17 MD1 MD2 18 19 RDY/P80 20 BGRNT/P81 21 BRQ/P82 WR0 24 WR1/P85 25 D16/P20 4 (Top view ...
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... CS0 14 NMI 15 HST 16 RST MD0 19 MD1 20 MD2 21 RDY/P80 22 BGRNT/P81 23 BRQ/P82 WR0 26 WR1/P85 27 D16/P20 28 D17/P21 29 D18/P22 30 MB91101/MB91101A (Top view (FPT-100P-M06) SO0/TRG1/PF1 SI0/TRG0/PF0 AN3 AN2 ...
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... MB91101/MB91101A PIN DESCRIPTION Pin no. Pin name LQFP* 1 QFP* 2 D16 to D23 P20 to P27 42, D24 to D30 D31 42, 45, A00 A01 to A15 A16 to A21, A22 64 67, A23 66, 69, P60 to P65 P66, ...
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... DW0 99 2 PB3 RAS1 100 3 PB4 EOP2 *1: FPT-100P-M05 *2: FPT-100P-M06 MB91101/MB91101A Circuit Description type L Chip select 0 output (“L” active) Chip select 1 output (“L” active) F Can be configured as a port when CS1 is not used. Chip select 2 output (“L” active) F Can be configured as a port when CS2 is not used. ...
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... MB91101/MB91101A Pin no. Pin name LQFP* 1 QFP* 2 CS1L PB5 1 4 DREQ2 CS1H PB6 2 5 DACK2 DW1 3 6 PB7 MD0 MD2 RST 13 16 HST 12 15 NMI INT0, INT1 95, 98 PE0, PE1 INT2 89 92 SC1 PE2 ...
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... PE7 SI0 76 79 TRG0 PF0 *1: FPT-100P-M05 *2: FPT-100P-M06 MB91101/MB91101A Circuit Description type External interrupt request input pin This pin is used for input during corresponding interrupt is enabled, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. ...
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... MB91101/MB91101A Pin no. Pin name LQFP* 1 QFP* 2 SO0 TRG1 77 80 PF1 SC0 OCPA3 78 81 PF2 SI1 79 82 TRG2 PF3 SO1 TRG3 80 83 PF4 SI2 81 84 OCPA1 PF5 *1: FPT-100P-M05 *2: FPT-100P-M06 10 Circuit Description type UART0 data output pin This function is available when UART0 data output is enabled. ...
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... FPT-100P-M05 *2: FPT-100P-M06 Note: In most of the above pins, I/O ports and resource I/O are multiplexed, e.g. P82 and BRQ. In case of conflict between output of I/O ports and resource I/O, priority is always given to the output of resource I/O. MB91101/MB91101A Circuit Description type UART2 data output pin This function is available when UART2 data output is enabled. ...
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... MB91101/MB91101A DRAM CONTROL PIN Data bus 16-bit mode Pin name 2CAS/1WR mode RAS0 Area 4 RAS RAS1 Area 5 RAS CS0L Area 4 CASL CS0H Area 4 CASH CS1L Area 5 CASL CS1H Area 5 CASH DW0 Area 4 WE DW1 Area Data bus 8-bit mode 1CAS/2WR mode — ...
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... N- P-ch N- Standby control signal P-ch D N-ch R MB91101/MB91101A • Oscillation feedback resistance 1 M approx. With standby control Clock input • CMOS level Hysteresis input Without standby control With pull-up resistance Digital input • CMOS level I/O With standby control Digital output Digital output Digital input • ...
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... MB91101/MB91101A (Continued) Type R F Standby control signal Circuit • CMOS level output • CMOS level Digital output P-ch N-ch Digital output Digital input • CMOS level input P-ch N-ch Digital input • CMOS level P-ch N-ch Digital input • CMOS level output P-ch Digital output ...
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... preferred to connect V and V CC possible also recommended to connect a ceramic capacitor as a bypass capacitor of about 0.1 F between position as close as possible to the MB91101 and MB91101A. SS MB91101/MB91101A or lower than V to input/output pin or applying voltage over CC SS ...
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... MB91101/MB91101A The MB91101 and MB91101A have an internal regulator. When using with 5 V power supply, supply pin and make sure to connect about 0.1 F bypass capacitor to V supply is needed for the A/D convertor. When using with 3 V power supply, connect both V to the 3 V power supply. ...
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... So it takes about 42 ms for the pin to be initialized from the oscillation starting at the source oscillation 12.5 MHz. Take care that the pin condition may be output condition at initial unstable condition. (With the MB91101A, however, initalization can be achieved in less than about 42 ms after turning on the internal power supply by maintaining the RST pin at "L" level.) 12 ...
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... MB91101/MB91101A BLOCK DIAGRAM RAM (2 Kbytes) Bit search module 3 DREQ0 to DREQ2 3 DMA controller (DMAC) DACK0 to (8 ch.) DACK2 3 EOP0 to EOP2 Bus converter (32 bits X0 Clock control unit X1 (Watchdog timer) RST HST 4 INT0 to INT3 Interrupt control unit NMI 4 AN0 to AN3 /AVRL 10-bit A/D converter SS AVRH (4 ch ...
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... Direct areas consists of the following areas dependent on accessible data sizes. Byte data access: 000 to 0FF H Half word data access: 000 to 1FF H Word data access: 000 to 3FF H MB91101/MB91101A 32 bytes) and the CPU linearly accesses the memory External ROM/external bus mode H Direct addressing area I/O area H See “ I/O MAP” I/O area H Access inhibited ...
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... MB91101/MB91101A 2. Registers The FR family has two types of registers; dedicated registers embedded on the CPU and general-purpose registers on memory. • Dedicated registers Program counter (PC): Program status (PS): Table base register (TBR): Holds top address of vector table used in EIT (Exceptional/Interrupt/Trap) Return pointer (RP): System stack pointer (SSP): Indicates system stack space. ...
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... ILM4 to ILM0: Register for holding interrupt level mask value. The value held by this register is used as a level mask. When an interrupt request issued to the CPU is higher than the level held by ILM, the interrupt request is accepted. ILM4 ILM3 ILM2 MB91101/MB91101A ILM1 ILM0 Interrupt level High-low High ...
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... MB91101/MB91101A GENERAL-PURPOSE REGISTERS R0 to R15 are general-purpose registers embedded on the CPU. These registers functions as an accumulator and a memory access pointer (field for indicating address). • Register bank structure R0 R1 R12 R13 R14 R15 Of the above 16 registers, following registers have special functions. To support the special functions, part of the instruction set has been sophisticated to have enhanced functions ...
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... M1 and M0. • Bus mode setting bits and functions Note: Because of without internal ROM, the MB91101 and MB91101A allow “10 MB91101/MB91101A Reset vector External data access area bus width External 8 bits External 16 bits — — ...
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... MB91101/MB91101A I/O MAP Address Abbreviation 0000 H 0001 PDR2 Port 2 data register H 0002 H to 0004 H 0005 PDR6 Port 6 data register H 0006 H 0007 H 0008 PDRB Port B data register H 0009 PDRA Port A data register H 000A H 000B PDR8 Port 8 data register H 000C H to 0011 H 0012 PDRE ...
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... H TMR2 16-bit timer register ch. 2 003F H 0040 H 0041 H 0042 H 16-bit reload timer control status register TMCSR2 ch. 2 0043 H 0044 H to 0077 H MB91101/MB91101A Register name Read/write (Reserved) R/W (Reserved) R/W R/W (Reserved) R/W (Reserved) Initial value XXXXXXXX B W XXXXXXXX B XXXXXXXX B R XXXXXXXX ...
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... MB91101/MB91101A Address Abbreviation 0078 H UTIM0/UTIMR0 U-TIMER register ch. 0/reload register ch. 0 0079 H 007A H 007B UTIMC0 U-TIMER control register ch 007C H UTIM1/UTIMR1 U-TIMER register ch. 1/reload register ch. 1 007D H 007E H 007F UTIMC1 U-TIMER control register ch 0080 H UTIM2/UTIMR2 U-TIMER register ch. 2/reload register ch. 2 0081 ...
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... Ch. 3 cycle setting register 00FB H 00FC H PDUT3 Ch. 3 duty setting register 00FD H 00FE PCNH3 Ch. 3 control status register H H 00FF PCNL3 Ch. 3 control status register L H MB91101/MB91101A Register name Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value ...
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... MB91101/MB91101A Address Abbreviation 0100 H to 01FF H 0200 H 0201 H DPDP DMAC parameter descriptor pointer 0202 H 0203 H 0204 H 0205 H DACSR DMAC control status register 0206 H 0207 H 0208 H 0209 H DATCR DMAC pin control register 020A H 020B H 020C H to 03E3 H 03E4 H 03E5 H ICHCR Instruction cache control register ...
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... Interrupt control register 16 H 0411 ICR17 Interrupt control register 17 H 0412 ICR18 Interrupt control register 18 H 0413 ICR19 Interrupt control register 19 H 0414 ICR20 Interrupt control register 20 H 0415 ICR21 Interrupt control register 21 H 0416 ICR22 Interrupt control register 22 H MB91101/MB91101A Register name Read/write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ...
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... MB91101/MB91101A Address Abbreviation 0417 ICR23 Interrupt control register 23 H 0418 ICR24 Interrupt control register 24 H 0419 ICR25 Interrupt control register 25 H 041A ICR26 Interrupt control register 26 H 041B ICR27 Interrupt control register 27 H 041C ICR28 Interrupt control register 28 H 041D ICR29 ...
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... AMD4 Area mode register 4 H 0624 AMD5 Area mode register 5 H 0625 DSCR DRAM signal control register H 0626 H RFCR Refresh control register 0627 H MB91101/MB91101A Register name Read/write (Reserved) R/W R/W R/W R/W R/W R/W Initial value ...
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... MB91101/MB91101A (Continued) Address Abbreviation 0628 H EPCR0 External pin control register 0 0629 H 062A H 062B EPCR1 External pin control register 1 H 062C H DMCR4 DRAM control register 4 062D H 062E H DMCR5 DRAM control register 5 062F H 0630 H to 07FD H 07FE LER Little endian register H 07FF MODR ...
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... UART2 receive complete UART0 transmit complete UART1 transmit complete UART2 transmit complete DMAC0 (complete, error) DMAC1 (complete, error) DMAC2 (complete, error) DMAC3 (complete, error) DMAC4 (complete, error) DMAC5 (complete, error) MB91101/MB91101A Interrupt number Interrupt level Decimal Hexadecimal Register 0 00 — — ...
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... MB91101/MB91101A Interrupt causes DMAC6 (complete, error) DMAC7 (complete, error) A/D converter (successive approxi- mation conversion type) 16-bit reload timer 0 16-bit reload timer 1 16-bit reload timer 2 PWM 0 PWM 1 PWM 2 PWM 3 U-TIMER 0 U-TIMER 1 U-TIMER 2 Reserved for system Reserved for system Reserved for system Reserved for system ...
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... Interrupt causes Reserved for system (used in REA- LOS*) Reserved for system (used in REA- LOS*) Used in INT instructions *: REALOS/FR uses interrupt number 0x40 and 0x41 for system code. MB91101/MB91101A Interrupt number Interrupt level Decimal Hexadecimal Register 64 40 — — ...
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... MB91101/MB91101A PERIPHERAL RESOURCES 1. I/O Ports There are 2 types of I/O port register structure; port data register (PDR0 to PDRF) and data direction register (DDR0 to DDRF), where bits PDR0 to PDRF and bits DDR0 to DDRF corresponds respectively. Each bit on the register corresponds to an external pin. In port registers input/output register of the port configures input/ output function of the port, while corresponding bit (pin) configures input/output function in data direction regis- ters. Bit “ ...
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... Address bit 7 000601 H 000605 H 00060B H 000609 H 000608 H 0000D2 H 0000D3 :Access W :Write only – :Unused MB91101/MB91101A Initial value bit 0 XXXXXXXX PDR2 XXXXXXXX PDR6 PDR8 - - XXX PDRA - XXXXXX PDRB XXXXXXXX PDRE XXXXXXXX PDRF XXXXXXXX Initial value bit DDR2 ...
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... MB91101/MB91101A 2. DMA Controller (DMAC) The DMA controller is a module embedded in FR family devices, and performs DMA (direct memory access) transfer. DMA transfer performed by the DMA controller transfers data without intervention of CPU, contributing to en- hanced performance of the system. • 8 channels • Mode: single/block transfer, burst transfer and continuous transfer: 3 kinds of transfer • ...
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... X :Indeterminate • Registers (DMA descriptor) Address bit 31 DPDP + 0 H DPDP + 0C H DPDP + 54 H MB91101/MB91101A bit 16 bit 0 Initial value XXXXXXXX XXXXXXXX DPDP XXXXXXXX DACSR ...
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... The UART is a serial I/O port for supporting asynchronous (start-stop system) communication or CLK synchro- nous communication, and it has the following features. The MB91101 and MB91101A consist of 3 channels of UART. • Full double double buffer • Both a synchronous (start-stop system) communication and CLK synchronous communication are available. ...
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... Receive error generate signal for DMA (to DMAC) MD1 MD0 SMR register CS0 SCKE SOE MB91101/MB91101A Transmit clock Receive clock Receive control circuit Transmit control circuit Start bit detect circuit Receive bit counter Transmit bit counter Receive parity counter SO (transmit data) ...
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... MB91101/MB91101A • Register configuration Address bit 15 0000001E H 00000022 H 00000026 H 0000001F H 00000023 H 00000027 H 0000001C H 00000020 H 00000024 H 0000001D H 00000021 H 00000002 :Access R/W :Readable and writable – :Unused X :Indeterminate 42 bit 8 bit 0 SCR0 SCR1 SCR2 SMR0 SMR1 SMR2 SSR0 SSR1 SSR2 SIDR0/SODR0 SIDR1/SIDR1 SIDR2/SIDR2 Initial value ...
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... The U-TIMER is a 16-bit timer for generating UART baud rate. Combination of chip operating frequency and reload value of U-TIMER allows flexible setting of baud rate. The U-TIMER operates as an interval timer by using interrupt issued on counter underflow. The MB91101 and MB91101A have 3 channel U-TIMER embedded on the chip. An interval counted. • Block diagram ...
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... The PWM timer can output high accurate PWM waves efficiently. The MB91101 and MB91101A have inner 4-channel PWM timers, and has the following features. • Each channel consists of a 16-bit down counter, a 16-bit data resister with a buffer for scyde setting, a 16-bit compare resister with a buffer for duty setting, and a pin controller. • ...
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... Block diagram (for one channel) PCSR Prescaler 16-bit down counter Start Peripheral clock Enable TRG input Edge detect Soft trigger MB91101/MB91101A PDUT cmp Load Borrow PPG mask Reverse bit IRQ PWM output 45 ...
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... MB91101/MB91101A • Register configuration bit 15 Address 000000DC H 000000DD H 000000DF H 000000E0 H 000000E1 H 000000E2 H 000000E3 H 000000E4 H 000000E5 H 000000E6 H 000000E7 H 000000E8 H 000000E9 H 000000EA H 000000EB H 000000EC H 000000ED H 000000EE H 000000EF H 000000F0 H 000000F1 H 000000F2 H 000000F3 H 000000F4 H 000000F5 H 000000F6 H 000000F7 H 000000F8 H 000000F9 H 000000FA H 000000FB H 000000FC H 000000FD H 000000FE H 000000FF ...
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... The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload timer, a prescaler for generating internal count clock and control registers. Internal clock can be selected from 3 types of internal clocks (divided by 2/8/32 of machine clock). The DMA transfer can be started by the interruption. The MB91101 and MB91101A consist of 3 channels of the 16-bit reload timer. • Block diagram 16 8 ...
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... MB91101/MB91101A • Register configuration Address bit 15 0000002E H 0000002F H 00000036 H 00000037 H 00000042 H 00000043 H 0000002A H 0000002B H 00000032 H 00000033 H 0000003E H 0000003F H 00000028 H 00000029 H 00000030 H 00000031 H 0000003C H 0000003D :Access R/W :Readable and writable R :Read only W :Write only – :Unused X :Indeterminate 48 bit 0 Initial value - - - - TMCSR0 ...
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... H 000003FC H 000003FE H 000003FD H 000003FF :Access R/W :Readable and writable R :Read only W :Write only X :Indeterminate MB91101/MB91101A Input latch Detection mode Single-detection data recovery Bit search circuit Search result bit 16 bit 0 Initial value XXXXXXXX XXXXXXXX BSD0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 XXXXXXXX XXXXXXXX ...
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... MB91101/MB91101A 8. 10-bit A/D Converter (Successive Approximation Conversion Type) The A/D converter is the module which converts an analog input voltage to a digital value, and it has following features. • Minimum converting time: 5.6 s/ch. (system clock: 25 MHz) • Inner sample and hold circuit • Resolution: 10 bits • Analog input can be selected from 4 channels by program. ...
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... Register configuration Address bit 15 0000003A H 0000003B H 00000038 H 00000039 :Access R/W :Readable and writable R :Read only – :Unused X :Indeterminate MB91101/MB91101A Initial value bit ADCS ADCR XXXXXXXX (R/ ( ...
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... MB91101/MB91101A 9. Interrupt Controller The interrupt controller processes interrupt acknowledgments and arbitration between interrupts. • Block diagram INT0 NMI RI00 * RI47 (DLYIRQ) DLYI* 1 *1: DLYI stands for delayed interrupt module (delayed interrupt generation block) (refer to the section “11. Delayed Interrupt Module” for detail). ...
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... ICR11 H 0000040C - - - 11111 H ICR12 0000040D - - - 11111 H ICR13 0000040E - - - 11111 H ICR14 0000040F - - - 11111 H ICR15 00000410 - - - 11111 H ICR16 ( ) :Access R/W :Readable and writable – :Unused MB91101/MB91101A Initial value Address bit 7 00000411 (R/ (R/W) 00000412 B H (R/W) 00000413 B H (R/W) 00000414 B H (R/W) 00000415 B H (R/W) 00000416 B H (R/W) ...
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... MB91101/MB91101A 10. External Interrupt/NMI Control Block The external interrupt/NMI control block controls external interrupt request signals input to NMI pin and INT0 to INT3 pins. Detecting levels can be selected from “H”, “L”, rising edge and falling edge (not for NMI pin). • Block diagram ...
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... Delayed interrupt module is a module which generates a interrupt for changing a task. By using this delayed interrupt module, an interrupt request to CPU can be generated/cancelled by the software. Refer to the section “9. Interrupt Controller” for delayed interrupt module block diagram. • Register configuration Address bit 7 00000430 :Access R/W :Readable and writable – :Unused MB91101/MB91101A bit 0 Initial value - - - - - - - DICR (R/ ...
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... MB91101/MB91101A 12. Clock Generation (Low-power consumption mechanism) The clock control block is a module which undertakes the following functions. • CPU clock generation (including gear function) • Peripheral clock generation (including gear function) • Reset generation and cause hold • Standby function (including hardware standby) • ...
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... H PDRR 00000483 H 00000484 GCR H 00000485 H PCTR 00000488 :Access R/W :Readable and writable W :Write only – :Unused X :Indeterminate MB91101/MB91101A bit 8 Initial value bit 0 1XXXX - STCR - - - - XXXXXXXX CTBR XXXXXXXX WPR (R/W) B (R/W) B (R/W) B (W) B (R/W) ...
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... MB91101/MB91101A 13. External Bus Interface The external bus interface controls the interface between the device and the external memory and also the external I/O, and has the following features. • 25-bit (32 Mbytes) address output • 6 independent banks owing to the chip select function. Can be set to anywhere on the logical address space for minimum unit 64 Kbytes. ...
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... Block diagram Address bus Data bus 32 32 Write buffer Read buffer Address buffer ASR AMR To TBT MB91101/MB91101A A-OUT Switch MUX Switch + Inpage Shifter 6 Comparator 8 DRAM control Underflow DMCR Refresh counter 3 External pin control block All blocks control 4 Registers and control ...
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... MB91101/MB91101A • Register configuration bit 31 Address 0000060C H 0000060D H 0000060E H 0000060F H 00000610 H 00000611 H 00000612 H 00000613 H 00000614 H 00000615 H 00000616 H 00000617 H 00000618 H 00000619 H 0000061A H 0000061B H 0000061C H 0000061D H 0000061E H 0000061F H AMD0 00000620 H 00000621 H 00000622 H 00000623 H AMD5 00000624 H 00000625 H 00000626 H 00000627 H 00000628 H 00000629 H 0000062B H 0000062C H 0000062D ...
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... Average output current is an average current for a 100 ms period at a corresponding pin. *5: Average total output current is an average current for a 100 ms period for all corresponding pins. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. MB91101/MB91101A Rating Symbol Min ...
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... MB91101/MB91101A 2. Recommended Operating Conditions ( operation (4 5.5 V) Parameter Power supply voltage Analog supply voltage Analog reference voltage Operating temperature Smoothing capacitor * the RAM state holding is not warranted in stop mode used for the bypass capacitor pin. CC *3: Use the ceramic capacitor or the capacitor whose frequency characteristic is equivalent to that of the ceramic capacitor ...
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... No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. MB91101/MB91101A Normal operation warranty range (T Net masked area are f . ...
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... MB91101/MB91101A 3. DC Characteristics Parameter Symbol Pin name Input pin ex- V cept for hyster- IH esis input HST, NMI, “H” level input RST, voltage PA1 to PA6, V IHS PB0 to PB7, PE0 to PE7, PF0 to PF7 Input other than V following sym- IL bols HST, NMI, “L” level input ...
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... CC CC Except for V Input capacitance 3.3 0.2 V (internal regulator output voltage) when using 5 V power supply when using 3 V power supply (internal regulator unused). MB91101/MB91101A Condition Min ...
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... MB91101/MB91101A 4. AC Characteristics Measurement Conditions • 5.0 V 10% CC Parameter “H” level input voltage “L” level input voltage “H” level output voltage “L” level output voltage V CC 0.0 V • 2 3 Parameter “H” level input voltage “ ...
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... Load capacitance - Delay characteristics (Output delay with reference to the internal MB91101/MB91101A 5 V Fall 3 V Rise 5 V Rise 3 V Fall 100 120 Load capacitance (pF) 67 ...
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... MB91101/MB91101A (1) Clock Timing Rating Symbol Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/falling time Internal operating clock f CPB frequency f CPP t CP Internal operating clock ...
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... Clock timing rating measurement conditions MB91101/MB91101A 0 0 ...
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... MB91101/MB91101A (2) Clock Output Timing Symbol Pin name Parameter t CYC Cycle time t CYC CLK CLK t CHCL CLK CLK t CLCH (internal operating clock cycle time): Refer to “(1) Clock Timing Rating.” CP CPB * frequency for 1 clock cycle including a gear cycle. CYC Use the doubler when CPU frequency is above 25 MHz ...
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... Source oscillation input (2) 2 dividing system (CHC bit of GCR set to “1”) (a) Gear 1 CLK pin t CYC CCK1/0: “00” t (b) Gear 1/2 CLK pin CYC CCK1/0: “01” (c) Gear 1/4 CLK pin CCK1/0: “10” (d) Gear 1/8 CLK pin CCK1/0: “11” MB91101/MB91101A t CYC t CYC 71 ...
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... MB91101/MB91101A • Ceramic oscillator applications Recommended circuit (2 contacts • Discreet type Oscillation frequency [MHz] CSA CST 5.00 to 6.30 CSA CST CSA CST 6.31 to 10.0 CSA CST CSA CST 10.1 to 13.0 CSA CST CSA 13.01 to 15.00 CST ( ): C and C internally connected 3 contacts type Recommended circuit (3 contacts Load capacitance ...
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... Reset/Hardware Standby Input Ratings Parameter Reset input time Hardware standby input time t (internal operating clock cycle time): Refer to “(1) Clock Timing Rating.” CP RST HST MB91101/MB91101A ( 5 Symbol Pin name Condition t RST t RSTL — ...
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... MB91101/MB91101A (4) Power on Supply Specifications (Power-on Reset) Symbol Pin name Parameter Power supply rising time Power supply shut off time t OFF t (clock cycle time): Refer to “(1) Clock Timing Rating.” < 0.2 V before the power supply rising Note: Sudden change in supply voltage during operation may initiate a power-on sequence ...
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... RDY input, add (t delay) to this rating. *2: Rating at a gear cycle of 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equation with 1/2, 1/4, 1/8, respectively. Equation: (2 – n/2) t – 25 CYC MB91101/MB91101A ( 5 ...
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... MB91101/MB91101A V OH CLK CS0 to CS5 A24 to A00 RD D31 to D16 WR0, WR1 D31 to D16 76 BA2 BA1 t CYC CHCSL CHAV CLRL RLDV t AVDV V IH Read CLWL CHDV V OH Write CHCSH ...
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... Ready Input Timing Symbol Parameter RDY set up time CLK t RDYS CLK RDY hold time t RDYH CLK RDY When wait(s) is inserted. RDY When no wait is inserted. MB91101/MB91101A ( 5 Value Pin name Condition Min RDY, CLK 15 — ...
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... MB91101/MB91101A (7) Hold Timing Symbol Pin name Condition Parameter t CHBGL BGRNT delay time t CHBGH Pin floating BGRNT time t XHAL BGRNT pin valid time t HAHV t (a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.” CYC Note : There is a delay time of more than 1 cycle from BRQ input to BGRNT change. ...
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... CYC *1: When Q1 cycle or Q4 cycle is extended for 1 cycle, add t *2: Rating at a gear cycle of 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equation with 1/2, 1/4, 1/8, respectively. Equation: (3 – n/2) t – 16 CYC MB91101/MB91101A ( 5 ...
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... MB91101/MB91101A Q1 t CYC V OH CLK RAS0 RAS1 t CLRAH CS0H CS0L CS1H CS1L A24 to A00 D31 to D16 DW0 DW1 V OH D31 to D16 CHDV1 CHRAL t CHCAV t CHRAV ROW address ...
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... CAS valid data input t CLDV time CAS data hold time t CADH t (a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.” CYC *: When Q4 cycle is extended for 1 cycle, add t MB91101/MB91101A ( 5 ...
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... MB91101/MB91101A Q5 CLK RAS0 RAS1 CS0H CS0L CS1H CS1L A24 to A00 COLUMN address V IH D31 to D16 Read V IL DW0 DW1 D31 to D16 CLCASL t CLCASH CHCAV COLUMN address CLDV CADH ...
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... Output data delay time t CHDV2 CAS Valid data input t CLDV2 time CAS data hold time t CADH2 t (a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.” CYC MB91101/MB91101A ( 5 Pin name Condition ...
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... MB91101/MB91101A t CYC Q1 CLK RAS0 V OH RAS1 t CLRAH2 CS0H CS0L CS1H CS1L A24 to A00 D31 to D16 DW0 DW1 V OH D31 to D16 CHDV2 *1: Q4S indicates Q4SR (Read) of Single DRAM cycle or Q4SW (Write) cycle. *2: indicates the timing when the bus cycle begins from the high speed page mode. ...
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... Output data delay time t CHDV3 CAS valid data input t CLDV3 time CAS data hold time t CADH3 t (a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.” CYC MB91101/MB91101A ( 5 Pin name Condition ...
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... MB91101/MB91101A t CYC Q1 CLK RAS0 V OH RAS1 t CLRAH3 CS0H CS0L CS1H CS1L A24 to A00 CHRL3 D31 to D16 DW0 DW1 V OH D31 to D16 CHDV3 *1: Q4H indicates Q4HR (Read) of Hyper DRAM cycle or Q4HW (Write) cycle. *2: indicates the timing when the bus cycle begins from the high speed page mode. ...
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... CHRAL t CLCASL CAS delay time t CLCASH R1 V CLK OH RAS0 RAS1 CS0H CS0L CS1H CS1L DW0 DW1 MB91101/MB91101A ( 5 Pin name Condition CLK, RAS0, RAS1 CLK, RAS0, RAS1 CLK, CS0H, CS0L, — CS1H, CS1L ...
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... MB91101/MB91101A (13) Self Refresh Symbol Parameter t CLRAH RAS delay time t CHRAL t CLCASL CAS delay time t CLCASH t CYC SR1 CLK RAS0 RAS1 CS0H CS0L CS1H CS1L 5 Pin name Condition CLK, RAS0, RAS1 CLK, RAS0, RAS1 CLK, CS0H, CS0L, — ...
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... Note : This rating is for AC characteristics in CLK synchronous mode. • Internal shift clock mode SCLK SLOV SOUT SIN • External shift clock mode SCLK SLOV SOUT SIN MB91101/MB91101A ( 5 Value Min — 8 ...
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... MB91101/MB91101A (15) Trigger System Input Timing Parameter Symbol t TRGH A/D start trigger input time t TRGL PWM external trigger input t TRGH time t TRGL cycle time of peripheral system clock CYCP ATG TRG0 to TRG3 5 Pin name Condition ...
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... V OH CLK DACK0 to DACK2 EOP0 to EOP2 (Normal bus) (Normal DRAM) DACK0 to DACK2 EOP0 to EOP2 (Single DRAM) (Hyper DRAM) t CHDL t CHEL V DREQ0 to DREQ2 IH MB91101/MB91101A ( 5 Pin name Condition DREQ0 to DREQ2 2 CLK, DACK0 to DACK2 CLK, ...
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... MB91101/MB91101A 5. A/D Converter Block Electrical Characteristics Parameter Resolution Total error Linearity error Differentiation linearity error Zero transition voltage Full-scale transition voltage Conversion time Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supply current Conversion variance between channels * ...
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... voltage for causing transition of digital output from (000 voltage for causing transition of digital output from (3FE) FST voltage for causing transition of digital output from (N – MB91101/MB91101A N+1 Actual characteristic V FST N (measured value (measured value) N–1 N– ...
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... MB91101/MB91101A • Total error A difference between actual value and theoretical value. The overall error includes zero-transition error, full- scale transition error and linearity error. 3FF 3FE 3FD 004 003 002 001 0.5 LSB’ AVRL Total error of digital output LSB’ (ideal value ’ ...
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... I characteristics CC CC Internal regulator is not used (V Icc (mA 2.4 2.7 3.0 V (V) CC Operating conditions : Source oscillation 12.5 MHz (crystal), divide-by-2 input, PLL : ON MB91101/MB91101A Internal regulator is used ( ...
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... MB91101/MB91101A ORDERING INFORMATION Part number MB91101APFV MB91101APF 96 Package 100-pin Plastic LQFP (FPT-100P-M05) 100-pin Plastic QFP (FPT-100P-M06) Remarks ...
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... FUJITSU LIMITED F100007S-c-4-6 C MB91101/MB91101A Note These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder 0.08(.003) Details of "A" part +0 ...
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... MB91101/MB91101A (Continued) 100-pin Plastic QFP (FPT-100P-M06) 23.90±0.40(.941±.016) * 20.00±0.20(.787±.008 INDEX 100 1 0.65(.026) "A" 2002 FUJITSU LIMITED F100008S-c-5 Note These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. ...
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... MB91101/MB91101A FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device ...