W83977AF Information Storage Devices, Inc, W83977AF Datasheet - Page 58

• Manufacturer Part Number: W83977AF
• Description: W83877TF Plus Kbc, Cir, RTC
• Manufacturer: Information Storage Devices, Inc

Bit 3: The UART interrupt output is enabled by setting this bit to a logic 1. In the diagnostic mode this
Bit 2: This bit is used only in the diagnostic mode. In the diagnostic mode this bit is internally
Bit 1: This bit controls the RTS output. The value of this bit is inverted and output to RTS .
Bit 0: This bit controls the DTR output. The value of this bit is inverted and output to DTR .
3.2.4
This register reflects the current state of four input pins for handshake peripherals such as a modem
and records changes on these pins.
Bit 7: This bit is the opposite of the DCD input. This bit is equivalent to bit 3 of HCR in loopback
Bit 6: This bit is the opposite of the RI input. This bit is equivalent to bit 2 of HCR in loopback mode.
Bit 5: This bit is the opposite of the DSR input. This bit is equivalent to bit 0 of HCR in loopback
Bit 4: This bit is the opposite of the CTS input. This bit is equivalent to bit 1 of HCR in loopback
Bit 3:
Bit 2: FERI. This bit indicates that the RI pin has changed from low to high state after HSR was read
Bit 1: TDSR. This bit indicates that the DSR pin has changed state after HSR was read by the CPU.
Bit 0: TCTS. This bit indicates that the CTS pin has changed state after HSR was read.
3.2.5
This register is used to control the FIFO functions of the UART.
bit is internally connected to the modem control input DCD .
connected to the modem control input RI .
mode.
mode.
mode.
by the CPU.
TDCD. This bit indicates that the DCD pin has changed state after HSR was read by the
CPU.
UART FIFO Control Register (UFR) (Write only)
Handshake Status Register (HSR) (Read/Write)
(bit 0 of HCR)
Aside from the above connections, the UART operates normally. This method allows the
CPU to test the UART in a convenient way.
RI and IRQ enable ( bit 3 of HCR)
7
DSR, RTS ( bit 1 of HCR)
6
5
4
3
2
DCD .
1
0
CTS, Loopback RI input ( bit 2 of HCR)
Clear to send (CTS)
Data set ready (DSR)
Ring indicator (RI)
Data carrier detect (DCD)
CTS toggling (TCTS)
RI falling edge (FERI)
DCD toggling (TDCD)
DSR toggling (TDSR)
W83977F/ W83977AF
Publication Release Date: January 1997
PRELIMINARY
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Revision 0.50