uaa2077ts NXP Semiconductors, uaa2077ts Datasheet - Page 3

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uaa2077ts

Manufacturer Part Number
uaa2077ts
Description
2 Ghz Image Rejecting Front-end
Manufacturer
NXP Semiconductors
Datasheet
Philips Semiconductors
BLOCK DIAGRAM
PINNING
2000 Apr 17
handbook, full pagewidth
V
n.c.
RFINA
RFINB
n.c.
LNAGND
SXON
n.c.
GND
RXON
LOINB
LOINA
V
LOGND
IFA
IFB
SYMBOL
CCLNA
CCLO
2 GHz image rejecting front-end
PIN
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
supply voltage for receive section
(LNA and IF parts)
not connected
RF input A (balanced)
RF input B (balanced)
not connected
ground for receive section (LNA and
IF parts)
SX mode enable input (see Table 1)
not connected
ground
RX mode enable input (see Table 1)
LO input B (balanced)
LO input A (balanced)
supply voltage for LO section
ground for LO section
IF output A (balanced)
IF output B (balanced)
LOGND
V CCLO
RFINA
RFINB
13
14
3
4
DESCRIPTION
V CCLNA
1
LNA
SXON
7
LNAGND
6
135
QUADRATURE
LOINB LOINA
Fig.1 Block diagram.
SHIFTER
GND
PHASE
11
9
n.c.
12
3
2, 5, 8
45
handbook, halfpage
RXON
LOCAL OSCILLATOR SECTION
135
45
10
LNAGND
V CCLNA
RFINA
RFINB
UAA2077TS
SXON
COMBINER
n.c.
n.c.
n.c.
RECEIVE SECTION
Fig.2 Pin configuration.
IF
1
2
3
4
5
6
7
8
UAA2077TS
FCA012
FCA011
15
16
Preliminary specification
16
15
14
13
12
11
10
9
UAA2077TS
IFA
IFB
IFB
IFA
LOGND
V CCLO
LOINA
LOINB
RXON
GND

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