hip6500 Intersil Corporation, hip6500 Datasheet - Page 8

• Manufacturer Part Number: hip6500
• Description: Multiple Linear Power Controller With Acpi Control Interface
• Manufacturer: Intersil Corporation

Functional Timing Diagrams
Figures 4 through 8 are timing diagrams, detailing the power
up/down sequences of all three outputs in response to the
status of the enable (EN3VDL, EN5VDL) and sleep-state
pins (S3, S5), as well as the status of the ATX supply.
The status of the EN3VDL and EN5VDL pins can only be
changed while in active (S0, S1) states, when the bias
supply (5VSB pin) is below POR level, or during chip
shutdown (SS pin shorted to GND); a status change of these
two pins while in a sleep state is ignored.
3V3DLSB
3V3DLSB
5VDLSB
5VDLSB
FIGURE 4. 3V
FIGURE 5. 3V
3V3DL
3V3DL
5VSB
5VDL
5VSB
5VDL
DLA
DLA
12V
12V
S3
S5
S3
S5
EN3VDL = 1, EN5VDL = 1
EN3VDL = 1, EN5VDL = 0
DUAL
DUAL
AND 5V
AND 5V
DUAL
DUAL
8
TIMING DIAGRAM FOR
TIMING DIAGRAM FOR
HIP6500
Not shown in these diagrams is the deglitching feature used
to protect against false sleep state tripping. Both S3 and S5
pins are protected against noise by a 2 s filter (typically 1 -
4 s). This feature is useful in noisy computer environments if
the control signals have to travel over significant distances.
Additionally, the S3 pin features a 200 s delay in
transitioning to sleep states. Once the S3 pin goes low, an
internal timer is activated. At the end of the 200 s interval, if
the S5 pin is low, the HIP6500 switches into S5 sleep state; if
the S5 pin is high, the HIP6500 goes into S3 sleep state.
3V3DLSB
3V3DLSB
5VDLSB
5VDLSB
FIGURE 6. 3V
FIGURE 7. 3V
3V3DL
3V3DL
5VSB
5VSB
5VDL
5VDL
DLA
DLA
12V
12V
S3
S5
S3
S5
EN3VDL = 0, EN5VDL = 1
EN3VDL = 0, EN5VDL = 0
DUAL
DUAL
AND 5V
AND 5V
DUAL
DUAL
TIMING DIAGRAM FOR
TIMING DIAGRAM FOR