hip6501a Intersil Corporation, hip6501a Datasheet - Page 7

• Manufacturer Part Number: hip6501a
• Description: Triple Linear Power Controller With Acpi Control Interface
• Manufacturer: Intersil Corporation

NOTE:
Very similarly, Table 2 details the fact that EN5VDL status
controls whether the 5V
NOTE:
As seen in Table 3, 2.5/3.3V
(Suspend-To-RAM), but not in S4/S5 state. The dual-voltage
support accommodates both SDRAM as well as RDRAM
type memories.
Additionally, the internal circuitry does not allow the
transition from an S3 (suspend to RAM) state to an S4/S5
(suspend to disk/soft off) state or vice versa. The only ‘legal’
transitions are from an active state (S0, S1) to a sleep state
(S3, S4/S5) and vice versa.
Functional Timing Diagrams
Figures 4-8 are timing diagrams, detailing the power
up/down sequences of all three outputs in response to the
status of the enable (EN3VDL, EN5VDL) and sleep-state
pins (S3, S5), as well as the status of the ATX supply.
The status of the EN3VDL and EN5VDL pins can only be
changed while in active (S0, S1) states, when the bias
supply (5VSB pin) is below POR level, or during chip
shutdown (SS pin shorted to GND); a status change of these
two pins while in a sleep state is ignored.
EN5VDL
5. Combination not allowed.
6. Combination not allowed.
R
10kΩ
10kΩ
10kΩ
10kΩ
1kΩ
1kΩ
1kΩ
1kΩ
SEL
TABLE 3. 2.5/3.3V
0
0
0
0
1
1
1
1
TABLE 2. 5V
S5
1
1
0
0
1
1
0
0
S5
1
1
0
0
1
1
0
0
DUAL
S3
1
0
1
0
1
0
1
0
S3
MEM
1
0
1
0
1
0
1
0
OUTPUT (V
DUAL
2.5/3.3V
OUTPUT (V
Note 6
Note 6
Note 5 Maintains Previous State
Note 5 Maintains Previous State
5VDL
2.5V
2.5V
3.3V
3.3V
MEM
0V
0V
5V
0V
0V
5V
5V
5V
plane supports sleep states.
7
MEM
output is maintained in S3
OUT3
S0, S1 STATES (Active)
S3
S4/S5
S0, S1 STATES (Active)
S3
S4/S5
OUT2
S0, S1 STATES (Active)
S3
Maintains Previous State
S4/S5
S0, S1 STATES (Active)
S3
Maintains Previous State
S4/S5
) TRUTH TABLE
COMMENTS
) TRUTH TABLE
COMMENTS
HIP6501A
Not shown in these diagrams is the de-glitching feature used
to protect against false sleep state tripping. Once the status
of the S3 pin changes, an internal timer is activated. If at the
end of the timeout period (typically 200µs) the input pins
present a valid state change request, then the controller
transitions to the new configuration. Otherwise, the
previously attained valid state is maintained until valid
control signals are received from the system. This particular
feature is useful in noisy computer environments if the
control signals have to travel over significant distances.
3V3DLSB
5VDLSB
3V3DLSB
5VDLSB
3V3DL
FIGURE 4. 3V
FIGURE 5. 3V
5VSB
5VDL
3V3DL
DLA
5VSB
5VDL
12V
DLA
S3
S5
12V
S3
S5
EN3VDL = 1, EN5VDL = 1
EN3VDL = 1, EN5VDL = 0
DUAL
DUAL
AND 5V
AND 5V
DUAL
DUAL
TIMING DIAGRAM FOR
TIMING DIAGRAM FOR
December 30, 2004
FN4749.6