lt3579iufd-trpbf Linear Technology Corporation, lt3579iufd-trpbf Datasheet - Page 13

• Manufacturer Part Number: lt3579iufd-trpbf
• Description: Lt3579/lt3579-1 6a Boost/inverting Dc/dc Converter With Fault Protection Features
• Manufacturer: Linear Technology Corporation

APPLICATIONS INFORMATION
BOOST CONVERTER COMPONENT SELECTION
Figure 6. Boost Converter – The Component Values Given Are
Typical Values for a 1MHz, 5V to 12V Boost
The LT3579 can be confi gured as a Boost converter as in
Figure 6. This topology allows for positive output voltages
that are higher than the input voltage. An external PMOS
(optional) driven by the GATE pin of the LT3579 can achieve
input or output disconnect during a FAULT event. A single
feedback resistor sets the output voltage. For output
voltages higher than 40V, see the Charge Pump topology
in the Charge Pump Aided Regulators section.
Table 1 is a step-by-step set of equations to calculate
component values for the LT3579 when operating as a
Boost converter. Input parameters are input and output
voltage, and switching frequency (V
respectively). Refer to the Appendix for further information
on the design equations presented in Table 1.
Variable Defi nitions:
V
V
DC = Power Switch Duty Cycle
f
I
I
R
using PMOS)
V
OSC
OUT
RIPPLE
5V
IN
IN
OUT
DSON_PMOS
= Input Voltage
= Switching Frequency
= Maximum Output Current
= Output Voltage
C
22μF
IN
= Inductor Ripple Current
100k
200k
R
86.6k
2.2μH
T
L1
= R
V
FAULT
SHDN
RT
SYNC
IN
SW1 SW2
DSON
LT3579
GND
CLKOUT
of External PMOS (set to 0 if not
30V, 4A
GATE
D1
SS
FB
V
C
C
0.1μF
SS
C
10μF
130k
OUT1
R
FB
C
47pF
F
IN
R
6.3k
OPTIONAL
GATE
, V
M
R
8k
1
C
OUT
C
2.2nF
C
37591 F06
and f
V
IN
V
12V
1.7A
OSC
C
10μF
OUT
OUT
Table 1. Boost Design Equations
Step 1:
Inputs
Step 2:
DC
Step 3:
L1
Step 4:
I
Step 5:
I
Step 6:
D1
Step 7:
C
C
Step 8:
C
Step 9:
R
Step 10:
R
Step 11:
PMOS
Note: The maximum design target for peak switch current is 6A and
is used in this table. The fi nal values for C
from the above equations in order to obtain desired load transient
performance for a particular application.
RIPPLE
OUT
OUT,
OUT1
IN
FB
T
Pick V
• Solve equations 1, 2, and 3.
• Choose the higher value between L
Only needed for input or output disconnect. See PMOS
Selection in the Appendix for information on sizing the PMOS
and the biasing resistor, R
C
OUT
L1 should never exceed L
C
C
IN
IN
=
IN
L
L
L
C
, V
=
=
MIN
MAX
TYP
OUT
R
C
8
OUT
PWR
T
•
1
=
=
I
=
=
f
OSC
, and f
OUT
=
(
(
I
87 6
DC
(
f
f
+
V
RIPPLE
V
OSC
OSC
V
I
IN
RIPPLE
IN
PARAMETERS/EQUATIONS
C
IN
• .
.
=
V
R
≅
f
4
VIN
0 005
LT3579/LT3579-1
OSC
f
OSC
R
– .
– .
OSC
⎛
⎜
⎝
•
FB
A f
– .
– ;
6
V
>
0 27
0 27
(
0 27
•
1
OUT
A
0 01
=
V
=
to calculate equations below.
•
V
. •
OUT
• 0 5 .
OSC
–
GATE
(
OUT
f
1 8
V
•
OSC
MAX
V
V
V
.
OUT
+
V
V
IN
I
IN
) )
)
RIPPLE
V
–
A
•
)
.
0 5
A
•
;
OUT
83 3
•
.
– . 0 27
in MHz and R in k
•
f
2
I
.
(
+
V
OSC
DC
(
AVG
1
– .
OUT
D
IN
2
.
V
I
40
–
OUT
C C
1 215
•
– . •
μA
+
TYP
– .
DC
and C
•
⎞
⎟ •
⎠
0 5
DC
>
•
0 5
V
0 27
L
I
•
.
f
)
1
OUT
and L
)
OSC
(
–
1
DC
V
•
I
V
OUT
6
IN
–
1
DC
V
A
)
•
DC
may deviate
MIN
• •
T
0 005
•
DC
.
R
)
D D SON PMOS
for L1.
Ω
•
13
_
V
IN
(1)
(2)
(3)
35791f
)