lm2633mtd National Semiconductor Corporation, lm2633mtd Datasheet - Page 32

• Manufacturer Part Number: lm2633mtd
• Description: Advanced Two-phase Synchronous Triple Regulator Controller For Notebook Cpus
• Manufacturer: National Semiconductor Corporation

www.national.com
Control Loop Design
The value of f
nators of Equation (35) and Equation (27) . The result is:
From the above expressions, it can be seen that the
control-output transfer function has three poles and one
zero. Of the three poles, one is a real pole (f
at low frequency, the other two are either complex conju-
gates that are located at half the switching frequency (f
are separated real poles, depending on the Q value. When Q
value is less than 0.5, the two high frequency poles will
become two real poles.
From Equation (34) it can be told that Q will become nega-
tive when m
unstable system because the control-output transfer function
will have a right-half-plane pole.
Example: L = 1.5 µH, C = 2 mF, R
V
S
The resulting gain plot is shown in Figure 9 as the asymptotic
plot. The plots of the actual gain and phase as computed by
Equation (27) are also shown.
in
e
= 0.25V,
= 10V, V
S
out
c
p
e
= 5.
can be determined by comparing the denomi-
<
= 1.6V, R = 0.4 . For LM2633, f = 250 kHz,
= 0.25V x 250kHz = 62.5mV/µs
f
n
R
1/(2D’). A negative Q value means an
= 250kHz ÷ 2 = 125kHz
j
= 10m
x 5 = 50m
e
= 9 m , R
(Continued)
p
) that is located
ds
= 10 m ,
n
(39)
(40)
), or
32
It should be noted that load resistance only changes the low
frequency gain. This causes the location of the low fre-
quency pole to change with load.
Frequency Compensation Design
The general purpose to compensate the loop is to meet
static and dynamic performance requirements while main-
taining stability. Loop gain is what is usually checked for
small-signal performance. Loop gain is equal to the product
of control-output transfer function (or so-called ’plant’) and
the output-control transfer function (i.e. the compensation
network transfer function). Different compensation schemes
result in different trade-offs among static accuracy, transient
response speed and degree of stability, etc.
Generally speaking it is a good idea to have a loop gain
slope that is −20dB/decade from a very low frequency to well
beyond cross-over frequency. The cross-over frequency
should not exceed one-fifth of the switching frequency, i.e.
50kHz in the case of LM2633. The higher the bandwidth, the
potentially faster the load transient response speed. How-
ever, if the duty cycle saturates during the load transient,
then further increasing the small signal bandwidth will not
help. In the context of CPU core or GTL bus power supply, a
small-signal bandwidth of 20kHz to 30kHz should be suffi-
cient if output capacitors are not just MLCs.
Since the control-output transfer function usually has very
limited low frequency gain (see Figure 9 ), it is a good idea to
place a pole in the compensation at zero frequency, so that
the low frequency gain especially the DC gain will be very
large. A large DC gain means high DC regulation accuracy
(i.e. DC voltage changes little with load or line variations).
The rest of the compensation scheme depends highly on the
plant shape. If a typical shape such as shown in Figure 9 is
assumed, then the following can be done to create a
−20dB/decade roll-off of the loop gain.
Place the first zero at f
second zero at f
−20dB/dec slope from zero frequency up to f
switching frequency).
Figure 10 shows the gain plot of such a two-pole two-zero
(more accurately, a lag-lag) compensation network, where
f
pole frequencies. The first pole f
quency.
z1
FIGURE 9. Example Control-Output Transfer Function
, f
z2
and f
p2
are the first zero, second zero and second
n
, then the resulting loop gain plot will be of
Bode Plot
p
, the second pole at f
p1
is located at zero fre-
20000863
n
z
, and the
(half the