xc1701lso20i Xilinx Corp., xc1701lso20i Datasheet - Page 5

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xc1701lso20i

Manufacturer Part Number
xc1701lso20i
Description
Configuration Proms
Manufacturer
Xilinx Corp.
Datasheet
Figure 2: Master Serial Mode. The one-time-programmable PROM supports automatic loading of configuration programs.
DS027 (v3.1) July 5, 2000
Product Specification
Multiple devices can be cascaded to support additional FPGAs. An early DONE inhibits the PROM data output one CCLK
RESET
* For mode pin connections,
refer to the appropriate FPGA data sheet.
R
(Output)
(Output)
CCLK
D
OUT
D
MODES*
RESET
IN
(Low Resets the Address Pointer)
FPGA
V
CC
D
DONE
CCLK
OUT
INIT
D
IN
cycle before the FPGA I/Os become active.
3.3V
www.xilinx.com
1-800-255-7778
4.7K
CLK
CE
OE/RESET
DATA
OPTIONAL
Daisy-chained
FPGAs with
Different
configurations
OPTIONAL
Slave FPGAs
with Identical
Configurations
V
V
XC1700E and XC1700L Series Configuration PROMs
CC
CC
PROM
V
PP
CEO
CLK
CE
OE/RESET
DATA
Cascaded
Memory
Serial
DS027_02_060100
5

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