xc1701lso20i Xilinx Corp., xc1701lso20i Datasheet

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xc1701lso20i

Manufacturer Part Number
xc1701lso20i
Description
Configuration Proms
Manufacturer
Xilinx Corp.
Datasheet
DS027 (v3.1) July 5, 2000
Features
DS027 (v3.1) July 5, 2000
Product Specification
One-time programmable (OTP) read-only memory
designed to store configuration bitstreams of Xilinx
FPGA devices
Simple interface to the FPGA; requires only one user
I/O pin
Cascadable for storing longer or multiple bitstreams
Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
XC17128E/EL, XC17256E/EL, XC1701 and XC1700L
series support fast configuration
Low-power CMOS Floating Gate process
XC1700E series are available in 5V and 3.3V versions
XC1700L series are available in 3.3V only
Available in compact plastic packages: 8-pin SOIC,
8-pin VOIC, 8-pin PDIP, 20-pin SOIC, 20-pin PLCC,
44-pin PLCC or 44-pin VQFP.
Programming support by leading programmer
manufacturers.
Design support using the Xilinx Alliance and
Foundation series software packages.
Guaranteed 20 year life data retention
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
RESET/
RESET
OE/
OE
or
Figure 1: Simplified Block Diagram (does not show programming circuit)
CLK
CE
R
V CC
V PP
GND
0
0
www.xilinx.com
1-800-255-7778
Address Counter
8
EPROM
Matrix
Cell
XC1700E and XC1700L Series
Configuration PROMs
Product Specification
Description
The XC1700 family of configuration PROMs provides an
easy-to-use, cost-effective method for storing large Xilinx
FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA D
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance or Foun-
dation series development system compiles the FPGA
design file into a standard Hex format, which is then trans-
ferred to most commercial PROM programmers.
Output
TC
OE
CEO
DATA
DS027_01_021500
IN
pin. The
1

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xc1701lso20i Summary of contents

Page 1

R DS027 (v3.1) July 5, 2000 Features • One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices • Simple interface to the FPGA; requires only one user I/O pin • Cascadable for storing longer or ...

Page 2

XC1700E and XC1700L Series Configuration PROMs Pin Description DATA Data output high-impedance state when either are inactive. During programming, the DATA pin is I/O. Note that OE can be programmed to be either active ...

Page 3

R Xilinx FPGAs and Compatible PROMs Configuration Device Bits XC4003E 53,984 XC4005E 95,008 XC4006E 119,840 XC4008E 147,552 XC4010E 178,144 XC4013E 247,968 XC4020E 329,312 XC4025E 422,176 XC4002XL 61,100 XC4005XL 151,960 XC4010XL 283,424 XC4013XL/XLA 393,632 XC4020XL/XLA 521,880 XC4028XL/XLA 668,184 XC4028EX 668,184 XC4036EX/XL/XLA ...

Page 4

XC1700E and XC1700L Series Configuration PROMs Controlling PROMs Connecting the FPGA device with the PROM. • The DATA output(s) of the of the PROM(s) drives the D input of the lead FPGA device. IN • The Master FPGA CCLK output ...

Page 5

OUT FPGA MODES* RESET RESET CCLK DONE * For mode pin connections, refer to the appropriate FPGA data sheet. (Low Resets the Address Pointer) CCLK (Output OUT (Output) Figure 2: Master Serial Mode. ...

Page 6

XC1700E and XC1700L Series Configuration PROMs Standby Mode The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high impedance state regardless of the state of the OE input. Table 1: Truth Table ...

Page 7

R XC1701, XC1736E, XC1765E, XC17128E and XC17256E Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Supply voltage relative to GND PP V Input voltage relative to GND IN V Voltage applied to High-Z output TS T ...

Page 8

XC1700E and XC1700L Series Configuration PROMs XC1704L, XC1702L, XC1701L, XC17512L, XC1765EL, XC17128EL and XC17256EL Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Supply voltage relative to GND PP V Input voltage relative to GND IN V ...

Page 9

R AC Characteristics Over Operating Condition CE RESET/OE CLK T CE DATA Symbol Description data delay data delay CE T CLK to data delay CAC data float delay ...

Page 10

XC1700E and XC1700L Series Configuration PROMs AC Characteristics Over Operating Condition When Cascading RESET/OE CE CLK DATA CEO Symbol Description (2,3) T CLK to data float delay CDF (3) T CLK to CEO delay OCK ( CEO ...

Page 11

... Operating Range/Processing ° ° Commercial ( + ° ° Industrial (T = – XC1701PD8C XC1702LVQ44C XC1701PC20C XC1702LPC44C XC1701SO20C XC1704LVQ44C XC1701PD8I XC1704LPC44C XC1701PC20I XC1702LVQ44I XC1701SO20I XC1702LPC44I XC1704LVQ44I XC1704LPC44I XC1701LPD8C XC17512LPD8C XC1701LPC20C XC17512LPC20C XC1701LSO20C XC17512LSO20C XC1701LPD8I XC17512LPD8I XC1701LPC20I XC17512LPC20I XC1701LSO20I XC17512LSO20I 11 ...

Page 12

XC1700E and XC1700L Series Configuration PROMs Marking Information Due to the small size of the commercial serial PROM packages, the complete ordering part number cannot be marked on the package. The XC prefix is deleted and the package code is ...

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