xc17s100avq44i Xilinx Corp., xc17s100avq44i Datasheet

xc17s100avq44i

Manufacturer Part Number

xc17s100avq44i

Description

Spartan-ii/spartan-iie Family Otp Configuration Proms Xc17s00a

Manufacturer

Xilinx Corp.

Datasheet

1.XC17S100AVQ44I.pdf (9 pages)

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DS078 (v1.8) November 18, 2002

Features

•

Introduction

The XC17S00A family of PROMs provide an easy-to-use,

cost-effective method for storing Spartan-II/Spartan-IIE

device configuration bitstreams.

When the Spartan device is in Master Serial mode, it

generates a configuration clock that drives the Spartan

PROM. A short access time after the rising clock edge, data

appears on the PROM DATA output pin that is connected to

the Spartan device D

the appropriate number of clock pulses to complete the

trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature,

application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may

require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties

or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.

DS078 (v1.8) November 18, 2002

Advance Product Specification

Notes:

Configuration one-time programmable (OTP) read-only

memory designed to store configuration bitstreams for

Spartan-II/Spartan-IIE FPGA devices

Simple interface to the Spartan device

Programmable reset polarity (active High or active

Low)

Low-power CMOS floating gate process

3.3V PROM

Due to the higher configuration bit requirements of the XC2S150E device, an XC17S200A PROM is required to configure this FPGA.

See XC17V00 series configuration PROMs data sheet at:

Spartan-II/IIE FPGA

XC2S150E

XC2S100E

XC2S200E

XC2S300E

XC2S400E

XC2S600E

XC2S50E

XC2S100

XC2S150

XC2S200

XC2S15

XC2S30

XC2S50

pin. The Spartan device generates

(1)

Configuration Bits

www.xilinx.com

1-800-255-7778

1,040,096

1,335,840

1,134,496

1,442,016

1,875,648

2,693,440

3,961,632

http://direct.xilinx.com/bvdocs/publications/ds073.pdf

197,696

336,768

559,200

781,216

630,048

863,840

Spartan-II/Spartan-IIE Family

OTP Configuration PROMs

(XC17S00A)

Advance Product Specification

•

configuration. Once configured, it disables the PROM.

When a Spartan device is in Slave Serial mode, the PROM

and the Spartan device must both be clocked by an

incoming signal.

For device programming, either the Xilinx Alliance or the

Spartan device design file into a standard HEX format

which is then transferred to most commercial PROM

programmers.

Available in compact plastic 8-pin DIP, 8-pin VOIC,

20-pin SOIC, or 44-pin VQFP packages.

Programming support by leading programmer

manufacturers.

Design support using the Xilinx Alliance and

Foundation series software packages.

Guaranteed 20-year life data retention

Compatible Spartan-II/IIE PROM

XC17S100A

XC17S150A

XC17S200A

XC17S100A

XC17S200A

XC17S300A

XC17V04

XC17S15A

XC17S30A

XC17S50A

(2)

Related parts for xc17s100avq44i

xc17s100avq44i Summary of contents

Page 1

R DS078 (v1.8) November 18, 2002 Features • Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams for Spartan-II/Spartan-IIE FPGA devices • Simple interface to the Spartan device • Programmable reset polarity (active High or active Low) • ...

Page 2

Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A) Pin Description Pins not listed are "no connects." Table 1: XC17S00A PROM Pinouts 8-pin PDIP (PD8) and 20-pin VOIC/TSOP SOIC Pin Name (VO8) (SO20) DATA 1 CLK 2 RESET/OE 3 (OE/RESET GND ...

Page 3

R Pinout Diagrams 1 DATA (D0) PD8/ 2 CLK VO8 Top View OE/RESET DATA(D0 CLK SO20 Top View ...

Page 4

Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A) Notes the DriveDone configuration option is not active, pull up DONE with a 3.3kΩ resistor. CCLK (Output OUT (Output) The one-time-programmable XC17S00A PROM in supports automatic loading of configuration ...

Page 5

R Standby Mode The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high-impedance state regardless of the state of the OE input. RESET OE/ RESET CLK Figure 2: Simplified ...

Page 6

Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A) XC17S15A, XC17S30A, XC17S50A, XC17S100A, XC17S150A, XC17S200A, and XC17S300A Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Input voltage with respect to GND IN V Voltage applied to High-Z output TS ...

Page 7

R AC Characteristics Over Operating Condition CE ESET/OE CLK DATA Symbol T RESET/OE to Data Delay Data Delay CE T CLK to Data Delay CAC T Data Hold From CE, RESET/OE, or ...

Page 8

Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A) Ordering Information Device Number XC17S15A XC17S30A XC17S50A XC17S100A Package Type XC17S150A XC17S200A PD8 VO8 XC17S300A SO20 = VQ44 = Spartan-II 3.3V Valid Ordering Combinations XC17S15APD8C XC17S15AVO8C XC17S15ASO20C XC17S15APD8I XC17S15AVO8I XC17S15ASO20I XC17S30APD8C XC17S30AVO8C XC17S30ASO20C XC17S30APD8I ...

Page 9

R Marking Information Due to the small size of the PROM package, the complete ordering part number cannot be marked on the package. Device Marking 17S15A 17S30A 17S50A 17S100A Package Mark 17S150A P 17S200A V 17S300A S VQ Revision History ...

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