m29f040 STMicroelectronics, m29f040 Datasheet - Page 4

• Manufacturer Part Number: m29f040
• Description: 4 Mbit 512kb X8, Uniform Block Single Supply Flash Memory
• Manufacturer: STMicroelectronics

M29F040
Table 3. Operations
Note:
Table 5. Block Protection Status
Note:
DEVICE OPERATION
Signal Descriptions
Address Inputs (A0-A18). The address inputs for
the memory array are latched during a write opera-
tion. The A9 address input is used also for the
Electronic Signature read and Block Protect veri-
fication. When A9 is raised to V
Manufacturer Code, Read Device Code or Verify
Block Protection is enabled depending on the com-
bination of levels on A0, A1 and A6. When A0, A1
and A6 are Low, the Electronic Signature Manufac-
turer code is read, when A0 is High and A1 and A6
are Low, the Device code is read, and when A1 is
High and A0 and A6 are low, the Block Protection
Status is read for the block addressed by A16, A17,
A18.
Data Input/Outputs (DQ0-DQ7). The data input is
a byte to be programmed or a command written to
the C.I. Both are latched when Chip Enable E and
Write Enable W are active. The data output is from
the memory Array, the Electronic Signature, the
Data Polling bit (DQ7), the Toggle Bit (DQ6), the
Error bit (DQ5) or the Erase Timer bit (DQ3). Ou-
puts are valid when Chip Enable E and Output
Enable G are active. The output is high impedance
4/31
Table 4. Electronic Signature
Read
Write
Output Disable
Standby
Manufact. Code
Device Code
Protected Block
Unprotected Block
Operation
Code
Code
X = V
SA = Address of block being checked
IL
or V
IH
V
V
E
V
V
IL
IL
E
IL
IL
V
V
G
V
V
IL
IL
G
IL
IL
V
V
V
V
E
IH
IL
IL
IL
ID
V
V
W
, either a Read
IH
IH
V
V
W
IH
IH
A0
V
V
IL
IL
V
A0
V
A1
V
V
IH
IL
IH
IH
V
V
V
G
X
IH
IH
IL
A6
V
V
A1
V
V
IL
IL
IL
IL
when the chip is deselected or the outputs are
disabled.
Chip Enable (E). The Chip Enable activates the
memory control logic, input buffers, decoders and
sense amplifiers. E High deselects the memory and
reduces the power consumption to the standby
level. E can also be used to control writing to the
command register and to the memory array, while
W remains at a low level. Addresses are then
latched on the falling edge of E while data is latched
on the rising edge of E. The Chip Enable must be
forced to V
Output Enable (G). The Output Enable gates the
outputs through the data buffers during a read
operation. G must be forced to V
Block Protect and Block Unprotect operations.
Write Enable (W). This input controls writing to the
Command Register and Address and Data latches.
Addresses are latched on the falling edge of W, and
Data Inputs are latched on the rising edge of W.
V
operations (Read, Program and Erase).
V
measurements.
CC
SS
A16
SA
SA
Ground. V
Supply Voltage. The power supply for all
A6
V
V
IL
IL
A17
SA
SA
ID
during Block Unprotect operations.
V
V
A9
A18
SS
SA
SA
ID
ID
V
V
V
W
X
IH
IH
IL
is the reference for all voltage
Addresses
Addresses
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Other
Other
Data Output
DQ0 - DQ7
Data Input
ID
Hi-Z
Hi-Z
level during
DQ0 - DQ7
DQ0 - DQ7
E2h
20h
01h
00h