br93lc66 ROHM Co. Ltd., br93lc66 Datasheet - Page 8

• Manufacturer Part Number: br93lc66
• Description: 4,096-bit Serial Electrically Erasable Prom
• Manufacturer: ROHM Co. Ltd.

(STATUS)
After time t
write command), if CS is set to HIGH, the write execute
= BUSY (LOW) and the command wait status READY
(HIGH) are output.
If in the command wait status (STATUS = READY), the
next command can be performed within the time t
Thus, if data is input via SK and DI with CS = HIGH in
the t
formed. To avoid this, make sure that DI = LOW when
CS = HIGH. (Caution is especially important when
common input ports are used.) This applies to all of the
write commands.
8
Memory ICs
E / W
period, erroneous operations may be per-
CS
CS
SK
DI
DO
CS
SK
DI
DO
following the fall of CS, after input of the
High-Z
High-Z
CS
SK
DI
DO
1
1
1
1
0
High-Z
0
2
2
1
0
1
BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV
Fig.5 Write all address cycle timing (WRAL)
A7
0
4
0
Fig.6 Write disable cycle timing (WDS)
Fig.4 Write cycle timing (WRITE)
A6
5
0
0
E / W
A1
0
.
A0
11
D15
D15 D14
(7) All address write (Figure 5)
With this command, the input 16-bit data is written
simultaneously to all of the addresses (128 words).
Rather than writing one word at a time, in succession,
data is written all at one time, enabling a write time of
t
(8) Write disable (Figure 6)
When the power supply is turned on, the IC enters the
write disable status. Similarly, when a write disable
command is issued, the IC enters the same status.
When in this status, all write commands are ignored,
but read commands may be executed.
In the write enable status, writing begins even if a write
command is entered accidentally. To prevent errors of
this type, we recommend executing a write disable
command after writing has been completed.
12
12
E / W
D14
.
D1
D1
D0
D0
27
27
t
t
CS
CS
t
t
E / W
E / W
BUSY
BUSY
t
t
STATUS
STATUS
SV
SV
READY
READY