at49lw080 ATMEL Corporation, at49lw080 Datasheet - Page 4

• Manufacturer Part Number: at49lw080
• Description: 8-megabit Firmware Hub Flash Memory
• Manufacturer: ATMEL Corporation

4. Pin Description
Table 4-1.
4
FWH[3:0]
FGPI[4:0]
Symbol
ID[3:0]
FWH4
RST
INIT
CLK
TBL
IC
AT49LW080
Pin Description
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Type
I/O
Table 4-1
with functions in both the Firmware Hub and A/A Mux interfaces. A/A Mux functionality for pins is
shown in bold in the description box for that pin. All pins are designed to be compliant with volt-
age of V
FWH
X
X
X
X
X
X
X
X
X
Interface
CC
details the usage of each of the device pins. Most of the pins have dual functionality,
+ 0.3V max, unless otherwise noted.
A/A Mux
X
X
Name and Function
INTERFACE CONFIGURATION PIN: This pin determines which interface is
operational. This pin is held high to enable the A/A Mux interface. This pin is held low to
enable the FWH interface. This pin must be set at power-up or before return from reset
and not changed during device operation. This pin is pulled down with an internal
resistor, with value between 20 and 100 kΩ. With IC high (A/A Mux mode), this pin will
exhibit a leakage current of approximately 200 µA. This pin may be floated, which will
select FWH mode.
INTERFACE RESET: Valid for both A/A Mux and FWH interface operations. When
driven low, RST inhibits write operations to provide data protection during power
transitions, resets internal automation, and tri-states pins FWH [3:0] (in FWH interface
mode). RST high enables normal operation. When exiting from reset, the device
defaults to read array mode.
PROCESSOR RESET: This is a second reset pin for in-system use. This pin is
internally combined with the RST pin. If this pin or RST is driven low, identical operation
is exhibited. This signal is designed to be connected to the chipset INIT signal (Max
voltage depends on the processor. Do not use 3.3V.)
A/A Mux = OE
33 MHz CLOCK for FWH INTERFACE: This input is the same as the PCI clock and
adheres to the PCI specification.
A/A Mux = R/C
FWH I/Os: I/O Communication.
A/A Mux = I/O[3:0]
FWH INPUT: Input Communication.
A/A Mux = WE
IDENTIFICATION INPUTS: These four pins are part of the mechanism that allows
multiple parts to be attached to the same bus. The strapping of these pins is used to
identify the component. The boot device must have ID[3:0] = 0000 and it is
recommended that all subsequent devices should use a sequential up-count strapping
(i.e., 0001, 0010, 0011, etc.). These pins are pulled down with internal resistors, with
values between 20 and 100 kΩ when in FWH mode. Any ID pins that are pulled high will
exhibit a leakage current of approximately 200 µA. Any pins intended to be low may be
left to float. In a single FWH system, all may be left floating.
A/A Mux = A[3:0]
FWH GENERAL PURPOSE INPUTS: These individual inputs can be used for
additional board flexibility. The state of these pins can be read through FWH registers.
These inputs should be at their desired state before the start of the PCI clock cycle
during which the read is attempted, and should remain at the same level until the end of
the read cycle. They may only be used for 3.3V signals. Unused FGPI pins must not be
floated.
A/A Mux = A[10:6]
TOP SECTOR LOCK: When low, prevents programming or sector erase to the highest
addressable sector (15), regardless of the state of the lock registers TBL high disables
hardware write protection for the top sector, though register-based protection still
applies. The status of TBL does not affect the status of sector-locking registers.
A/A Mux = A4
1966G–FLASH–3/05