at49lw080 ATMEL Corporation, at49lw080 Datasheet - Page 21

• Manufacturer Part Number: at49lw080
• Description: 8-megabit Firmware Hub Flash Memory
• Manufacturer: ATMEL Corporation

8. A/A Mux Interface
8.1
8.2
8.3
8.4
1966G–FLASH–3/05
Bus Operation
Output Disable/Enable
Row/Column Addresses
RDY/BUSY
The following information applies only to the AT49LW080 when in A/A Mux Mode. Information
on FWH Mode (the standard operating mode) is detailed earlier in this document. Electrical
characteristics in A/A Mux Mode are provided on pages starting from
The AT49LW080 is designed to offer a parallel programming mode for faster factory program-
ming. This mode, called A/A Mux Mode, is selected by having this IC pin high. The IC pin is
pulled down internally in the AT49LW080, so a modest current should be expected to be drawn
(see
the component: R/C, OE, WE, and RST. R/C is the A/A Mux control pin used to latch row and
column addresses. OE is the data output control pin (I/O0 - I/O7), drives the selected memory
data onto the I/O bus, when active WE and RST must be at V
All A/A Mux bus cycles can be conformed to operate on most automated test equipment and
PROM programmers.
Notes:
With OE at a logic-high level (V
placed in the high-impedance state. With OE at a logic-low level (V
enabled. Output pins I/O0 - I/O7 are placed in a output-drive state.
R/C is the A/A Mux control pin used to latch row (A0 - A10) and column addresses (A11 - A19).
R/C latches row addresses on the falling edge and column addresses on the rising edge.
An open drain Ready/Busy output pin provides a hardware method of detecting the end of a pro-
gram or erase operation. RDY/Busy is actively pulled low during the internal program and erase
cycles and is released at the completion of the cycle.
Mode
Read
Output Disable
Product ID Entry
Write
Table 4-1 on page 4
(4)(5)(6)
(1)(2)(6)
1. When V
2. X can be V
3. See
4. Command writes involving sector erase or program are reliably executed when V
5. Refer to “A/A Mux Read-only Operations” for valid D
6. V
pin. See the “DC Characteristics” for V
and V
min = 0.5V, V
IH
(6)
and V
Table 7-1 on page 17
(6)
CC
PP
= V
IL
≤ V
IL
refer to the DC characteristics associated with Flash memory output buffers: V
CC
or V
IL
PPLK
± 0.3V.
max = 0.8V, V
RST
for further information). Four control pins dictate data flow in and out of
V
V
V
V
IH
IH
IH
IH
IH
, the memory contents can be read, but not altered.
for control and address input pins and V
IH
), the device outputs are disabled. Output pins I/O0 - I/O7 are
for Product ID Entry data and addresses.
OE
V
V
V
V
IH
IH
IH
IL
IL
min = 2.0V, V
PPLK
WE
V
V
V
V
IH
IH
IH
and V
IL
IH
max = V
PPH1/2
Address
IN
during a write operation.
voltages.
CC
(3)
X
X
X
IH
.
+ 0.5V.
PPLK
or V
page 28
IL
), the device outputs are
V
PPH1/2
AT49LW080
X
X
X
X
PP
for the VPP supply
I/O0 - I/O7
PP
High-Z
Note 3
D
= V
D
OUT
IN
PPH1/2
IL
21