hmp8190 Intersil Corporation, hmp8190 Datasheet - Page 22

• Manufacturer Part Number: hmp8190
• Description: Ntsc/pal Video Encoder
• Manufacturer: Intersil Corporation

Pinout
Pin Descriptions
HSYNC
VSYNC
P0-P15
BLANK
NAME
FIELD
RESV
CLK2
CLK
PIN
NC
58, 55-43,
32-27, 23,
NUMBER
38, 37
PIN
22
21
34
35
36
33
39
41
22
NTSC/PAL
OUTPUT
INPUT/
GND
GND
GND
GND
GND
GND
GND
GND
VAA
VAA
VAA
VAA
VAA
I/O
I/O
I/O
I/O
O
I
I
I
I
C
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Pixel Input Pins. See Table 1. Any pixel inputs not used should be connected to GND.
No Connect Pins. These pins are not used. They may be left floating or may be connected
to GND.
This pin is reserved and should be connected to GND.
FIELD Output. The field output indicates that the encoder is outputting the odd or even video
field. The polarity of FIELD is programmable.
Horizontal Sync Input/Output. As an input, this pin must be asserted during the horizontal
sync intervals. If it occurs early, the line time will be shortened. If it occurs late, the line time
will be lengthened by holding the outputs at the front porch level. As an output, it is asserted
during the horizontal sync intervals. The polarity of HSYNC is programmable. If not driven,
the circuit for this pin should include a 4-12k pull up resistor connected to VAA.
Vertical Sync Input/Output. As an input, this pin must be asserted during the vertical sync
intervals. If it occurs early, the field time will be shortened. If it occurs late, the field time will
be lengthened by holding the outputs at the blanking level. As an output, it is asserted during
the vertical sync intervals. The polarity of VSYNC is programmable. If not driven, the circuit
for this pin should include a 4-12k pull up resistor connected to VAA.
Composite Blanking Input/Output. As an input, this pin must be asserted during the horizon-
tal and vertical blanking intervals. As an output, it is asserted during the horizontal and ver-
tical blanking intervals. The polarity of BLANK is programmable. If not driven, the circuit for
this pin should include a 4-12k pull up resistor connected to VAA.
1x Pixel Clock Input/Output. As an input, this clock must be free-running and synchronous
to the clock signal on the CLK2 pin. As an output, this pin may drive a maximum of one LS
TTL load. CLK is generated by dividing CLK2 by two or four, depending on the mode. If not
driven, the circuit for this pin should include a 4-12k pull up resistor connected to VAA.
2x Pixel Clock Input. This clock must be a continuous, free-running clock.
HMP8190, HMP8191
HMP8190/HMP8191
TOP VIEW
(PQFP)
DESCRIPTION
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P8
P9
P10
P11
P12
P13
GND
CLK2
VAA
CLK
P14
P15
VSYNC
HSYNC
FIELD
BLANK