hmp8190 Intersil Corporation, hmp8190 Datasheet - Page 20

• Manufacturer Part Number: hmp8190
• Description: Ntsc/pal Video Encoder
• Manufacturer: Intersil Corporation

NUMBER
NUMBER
NUMBER
NUMBER
NUMBER
BIT
BIT
BIT
BIT
BIT
7-0
7-1
7-0
7-0
7-4
0
2
LSB Assert BLANK
Output Signal
(Vertical)
Reserved
MSB Assert BLANK
Output Signal
(Vertical)
Negate BLANK
Output Signal
(Vertical)
Field Detect
Window Size Low
Half Line Count
Reset Value
VSYNC Edge
Select
FUNCTION
FUNCTION
FUNCTION
FUNCTION
FUNCTION
20
This 8-bit register is cascaded with Start V_Blank High Register to form a 9-bit
start_vertical_blank register. During normal operation, it specifies the line number (n) to start
ignoring pixel input data (and what line number to start blanking the output video) each odd
field; for even fields, it occurs on line (n + 262) or (n + 313).
The leading edge of VSYNC at the start of an odd field is count 000
follow standard NTSC or PAL line numbering). This register is ignored unless BLANK is con-
figured as an output.
This 1-bit register is cascaded with Start V_Blank Low Register to form a 9-bit
start_vertical_blank register. This register is ignored unless BLANK is configured as an output.
During normal operation, this 8-bit register specifies the line number (n) to start inputting pixel
input data (and what line number to start generating active output video) each odd field; for
even fields, it occurs on line (n + 262) or (n + 313).
The leading edge of VSYNC at the start of an odd field is count 000
follow standard NTSC or PAL line numbering). This register is ignored unless BLANK is con-
figured as an output.
This 8-bit register is cascaded with Field Detect Window Size High to form a 9-bit Field Detect
Window Size value. The value specifies the number of 1x clock cycles in the detection window
before and after the selected edge of VSYNC. It may range from 0 to 511. If the leading edge
of HSYNC occurs within the window, it is the start of an odd or even field, as specified by the
FIELD Detect Select bit. This register is ignored unless HSYNC and VSYNC are configured
as inputs.
These bits specify the value to load to the vertical half line counter when the selected edge of
VSYNC. The value is ignored when HSYNC and VSYNC are configured as outputs.
This bit specifies whether the encoder uses the leading or trailing edge of VSYNC to determine
the field and to reset the half line counter. It is ignored unless HSYNC and VSYNC are config-
ured as inputs.
0 = leading edge
1 = trailing edge
TABLE 36. START V_BLANK HIGH REGISTER
TABLE 35. START V_BLANK LOW REGISTER
TABLE 38. FIELD CONTROL REGISTER 1
TABLE 39. FIELD CONTROL REGISTER 2
TABLE 37. END V_BLANK REGISTER
HMP8190, HMP8191
SUB ADDRESS = 23
SUB ADDRESS = 24
SUB ADDRESS = 25
SUB ADDRESS = 26
SUB ADDRESS = 27
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
H
H
H
H
H
H
H
(note that this does not
(note that this does not
0000000
RESET
RESET
RESET
RESET
RESET
00000
STATE
STATE
STATE
STATE
STATE
03
13
80
1
0
B
B
H
H
H
B
B