hmp8156a Intersil Corporation, hmp8156a Datasheet - Page 22

• Manufacturer Part Number: hmp8156a
• Description: Ntsc/pal Video Encoder
• Manufacturer: Intersil Corporation

NUMBER
NUMBER
NUMBER
NUMBER
BIT
BIT
BIT
BIT
7-0
7-0
7-1
7-0
0
Negate BLANK
Output Signal
(Horizontal)
Assert BLANK
Output Signal
(Vertical)
Reserved
Assert BLANK
Output Signal
(Vertical)
Negate BLANK
Output Signal
(Vertical)
FUNCTION
FUNCTION
FUNCTION
FUNCTION
22
This 8-bit register specifies the horizontal count (in 1X clock cycles) at which to start inputting
pixel data each scan line. The leading edge of HSYNC is count 000
unless BLANK is configured as an output.
This 8-bit register is cascaded with Start V_Blank High Register to form a 9-bit
start_vertical_blank register. During normal operation, it specifies the line number (n) to start
ignoring pixel input data (and what line number to start blanking the output video) each odd
field; for even fields, it occurs on line (n + 262) or (n + 313).
During SIF input mode, the register value (n) specifies the line number to start ignoring pixel
input data each noninterlaced input frame. The output video will be blanked starting on line
number (n) each odd field; for even fields, it occurs on line (n + 262) or (n + 313).
The leading edge of VSYNC at the start of an odd field is count 000
follow standard NTSC or PAL line numbering). This register is ignored unless BLANK is con-
figured as an output.
This 1-bit register is cascaded with Start V_Blank Low Register to form a 9-bit
start_vertical_blank register. This register is ignored unless BLANK is configured as an output.
During normal operation, this 8-bit register specifies the line number (n) to start inputting pixel
input data (and what line number to start generating active output video) each odd field; for
even fields, it occurs on line (n + 262) or (n + 313).
During SIF input mode, the register value (n) specifies the line number to start inputting pixel
input data each noninterlaced input frame. The output video will be active starting on line num-
ber (n) each odd field; for even fields, it occurs on line (n + 262) or (n + 313).
The leading edge of VSYNC at the start of an odd field is count 000
follow standard NTSC or PAL line numbering). This register is ignored unless BLANK is con-
figured as an output.
TABLE 27. START V_BLANK HIGH REGISTER
TABLE 26. START V_BLANK LOW REGISTER
TABLE 25. END H_BLANK REGISTER
TABLE 28. END V_BLANK REGISTER
HMP8154, HMP8156A
SUB ADDRESS = 22
SUB ADDRESS = 23
SUB ADDRESS = 24
SUB ADDRESS = 25
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
H
H
H
H
H
H
H
. This register is ignored
(note that this does not
(note that this does not
November 4, 2005
0000000
RESET
RESET
RESET
RESET
STATE
STATE
STATE
STATE
7A
03
13
1
B
H
H
H
4343.4
B