hmp8156a Intersil Corporation, hmp8156a Datasheet - Page 21

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hmp8156a

Manufacturer Part Number
hmp8156a
Description
Ntsc/pal Video Encoder
Manufacturer
Intersil Corporation
Datasheet

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NUMBER
NUMBER
NUMBER
NUMBER
NUMBER
NUMBER
BIT
BIT
BIT
BIT
BIT
BIT
7-0
7-0
7-0
7-0
7-0
7-2
1-0
Line 21 Caption
Data
(First Byte)
Line 21 Caption
Data
(Second Byte)
Line 284 Caption
Data
(First Byte)
Line 284 Caption
Data
(Second Byte)
Assert BLANK
Output Signal
(Horizontal)
Reserved
Assert BLANK
Output Signal
(Horizontal)
FUNCTION
FUNCTION
FUNCTION
FUNCTION
FUNCTION
FUNCTION
21
This register is cascaded with the closed caption_21B data register and they are read out se-
rially as 16 bits during line 18, 21, or 22 if line 21 captioning is enabled. Bit D0 of the 21A data
register is shifted out first.
This register is cascaded with the closed caption_21A data register and they are read out se-
rially as 16 bits during line 18, 21, or 22 if line 21 captioning is enabled. Bit D0 of the 21A data
register is shifted out first.
This register is cascaded with the closed caption_284B data register and they are read out se-
rially as 16 bits during line 281, 284, or 335 if line 284 captioning is enabled. Bit D0 of the 284A
data register is shifted out first.
This register is cascaded with the closed caption_284A data register and they are read out se-
rially as 16 bits during line 281, 284, or 335 if line 284 captioning is enabled. Bit D0 of the 284A
data register is shifted out first.
This 8-bit register is cascaded with Start H_Blank High Register to form a 10-bit
start_horizontal_blank register. It specifies the horizontal count (in 1X clock cycles) at which
to start ignoring pixel data each scan line. The leading edge of HSYNC is count 020
register is ignored unless BLANK is configured as an output.
This 2-bit register is cascaded with Start H_Blank Low Register to form a 10-bit
start_horizontal_blank register. It specifies the horizontal count (in 1x clock cycles) at which to
start ignoring pixel data each scan line. The leading edge of HSYNC is count 020
ister is ignored unless BLANK is configured as an output.
TABLE 21. CLOSED CAPTION_284A DATA REGISTER
TABLE 22. CLOSED CAPTION_284B DATA REGISTER
TABLE 19. CLOSED CAPTION_21A DATA REGISTER
TABLE 20. CLOSED CAPTION_21B DATA REGISTER
TABLE 24. START H_BLANK HIGH REGISTER
TABLE 23. START H_BLANK LOW REGISTER
HMP8154, HMP8156A
SUB ADDRESS = 10
SUB ADDRESS = 11
SUB ADDRESS = 12
SUB ADDRESS = 13
SUB ADDRESS = 20
SUB ADDRESS = 21
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
H
H
H
H
H
H
H
. This reg-
H
. This
November 4, 2005
000000
RESET
RESET
RESET
RESET
RESET
RESET
STATE
STATE
STATE
STATE
STATE
STATE
4A
80
80
80
80
11
H
H
H
H
B
H
4343.4
B

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