mc68hc908bd48 Freescale Semiconductor, Inc, mc68hc908bd48 Datasheet - Page 225

• Manufacturer Part Number: mc68hc908bd48
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

16.6.5 Sync Processor Control Register 1 (SPCR1)
MC68HC908BD48
Freescale Semiconductor
—
Rev. 2.1
Address:
LVSIE — Low VSync Interrupt Enable
LVSIF — Low VSync Interrupt Flag
HPS[1:0] — HSYNC input Detection Pulse Width
Reset:
Read:
Write:
When this bit is set, the LVSIF flag is enabled to generate an interrupt
request to the CPU. When LVSIE is cleared, the LVSIF flag is
prevented from generating an interrupt request to the CPU. Reset
clears this bit.
This read-only bit is set when the value of VFR is higher than $C00
(vertical frame frequency below 40.7Hz). LVSIF generates an
interrupt request to the CPU if the LVSIE is also set. This bit is cleared
by writing a "0" to it or reset.
These two bits control the detection pulse width of HSYNC input.
Reset clears these two bits, setting a default middle frequency of
HSYNC input.
Figure 16-9. Sync Processor Control Register 1 (SPCR1)
1 = Low Vsync interrupt enabled
0 = Low Vsync interrupt disabled
1 = Vertical frequency is below 40.7Hz
0 = Vertical frequency is higher than 40.7Hz
HPS1
$0046
LVSIE
Bit 7
Table 16-8. HSYNC Polarity Detection Pulse Width
0
1
0
0
= Unimplemented
LVSIF
Sync Processor
6
0
0
HPS1
5
0
HPS0
X
0
1
HPS0
4
0
R
R
3
0
Polarity Detection Pulse Width
Long > 14µs and Short < 12µs
Long > 3.5µs and Short < 3µs
Long > 7µs and Short < 6µs
= Reserved
R
2
0
ATPOL
Sync Processor
1
0
Data Sheet
FSHF
Bit 0
0
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