mc68hc908bd48 Freescale Semiconductor, Inc, mc68hc908bd48 Datasheet - Page 136

• Manufacturer Part Number: mc68hc908bd48
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Timer Interface Module (TIM)
10.8 TIM During Break Interrupts
10.9 I/O Signals
Data Sheet
136
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the break flag control register (BFCR) enables software to clear status
bits during the break state. (See
(SBFCR).)
To allow software to clear status bits during a break interrupt, write a
logic one to the BCFE bit. If a status bit is cleared during the break state,
it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic zero to the
BCFE bit. With BCFE at logic zero (its default state), software can read
and write I/O registers during the break state without affecting status
bits. Some status bits have a two-step read/write clearing procedure. If
software does the first step on such a bit before the break, the bit cannot
change during the break state as long as BCFE is at logic zero. After the
break, doing the second step clears the status bit.
Port E shares one of its pins with the TIM. The TIM channel I/O pin is
PTE0/SOG/TCH0.
TCH0 pin is programmable independently as an input capture pin or an
output compare pin. It also can be configured as a buffered output
compare or buffered PWM pin.
Timer Interface Module (TIM)
7.8.3 SIM Break Flag Control Register
MC68HC908BD48
Freescale Semiconductor
—
Rev. 2.1