ade7953 Analog Devices, Inc., ade7953 Datasheet - Page 30

• Manufacturer Part Number: ade7953
• Description: Single Phase, Multifunction Metering Ic With Neutral Current Measurement Ade7953
• Manufacturer: Analog Devices, Inc.

ADE7953
APPARENT POWER CALCULATION
Apparent power is defined as the maximum power that can be
delivered to a load. VRMS and IRMS are the effective voltage
and current delivered to the load, respectively. The apparent
power can, therefore, be defined as the product of VRMS and
IRMS. This relationship is independent of the phase angle
between the voltage and current.
Equation 26 provides an expression for the instantaneous
apparent power signal in an ac signal.
The ADE7953 computes the apparent power simultaneously
on Current Channel A and Current Channel B and stores the
resulting measurements in the AVA (Address 0x210 and
Address 0x310) and BVA (Address 0x211 and Address 0x311)
registers, respectively.
The apparent power measurement is taken over a bandwidth
of 1.23 kHz and includes the effects of any harmonics within
that range. The apparent power registers are updated at a rate of
6.99 kHz and can be read using the waveform sampling mode
(see the Instantaneous Powers and Waveform Sampling section).
APPARENT ENERGY CALCULATION
The apparent energy is given as the integral of the apparent
power.
The ADE7953 achieves the integration of the apparent power
signal in two stages. In the first stage, the apparent power
signals are accumulated in an internal 48-bit register every
143 μs (6.99 kHz) until an internal fixed threshold is reached.
When this threshold is reached, a pulse is generated and is
accumulated in 24-bit, user accessible accumulation registers.
The internal threshold results in a maximum accumulation rate
of approximately 210 kHz with full-scale inputs.
P(t) = V(t) × I(t)
P(t) = VRMS × IRMS × cos( θ ) −
VRMS × IRMS × cos( 2ωt + θ )
V(t)
I(t)
Apparent
=
=
2
2
×
Energy
×
IRMS
VRMS
=
×
×
sin(
∫
sin(
CURRENT RMS
Apparent
CHANNEL
VOLTAGE
ωt
A OR B
ωt
RMS
+
)
θ
)
Power(t)dt
APPARENT
POWER
SIGNAL
Figure 55. Apparent Energy Accumulation Signal Chain
xVAGAIN
(23)
(24)
(25)
(26)
(27)
Rev. 0 | Page 30 of 68
+
xVAOS
+
48
ACCUMULATION
FIXED INTERNAL
THRESHOLD
INTERNAL
This process occurs simultaneously on Current Channel A and
Current Channel B, and the resulting readings can be read in the
24-bit APENERGYA (Address 0x222 and Address 0x322) and
APENERGYB (Address 0x223 and Address 0x323) registers.
Note that the apparent energy register contents roll over to full-
scale negative (0x800000) and continue to increase in value
when the power or energy flow is positive. Conversely, if the
power is negative, the energy register underflows to full-scale
positive (0x7FFFFF) and continues to decrease in value.
APENERGYA and APENERGYB are read-with-reset registers
by default. This means that the contents of these registers are
reset to 0 after a read operation. This feature can be disabled
by clearing Bit 6 (RSTREAD) of the LCYCMODE register
(Address 0x004).
The ADE7953 includes two sets of interrupts that are triggered
when the apparent energy register is half full (positive or
negative) or when an overflow or underflow condition occurs.
The first set of interrupts is associated with the Current
Channel A apparent energy, and the second set of interrupts is
associated with the Current Channel B apparent energy.
These interrupts are disabled by default and can be enabled by
setting the VAEHFA and VAEOFA bits in the IRQENA register
(Address 0x22C and Address 0x32C) for Current Channel A,
and the VAEHFB and VAEOFB bits in the IRQENB register
(Address 0x22F and Address 0x32F) for Current Channel B.
Apparent Energy Integration Time Under Steady Load
The discrete time sample period (T) for the accumulation
registers is 4.76 μs (1/210 kHz). With full-scale sinusoidal
signals on the analog inputs, a pulse is generated and added
to the APENERGYA and APENERGYB registers every 4.76 μs,
assuming that the AVAGAIN and BVAGAIN registers are set
to 0x00. The maximum positive value that can be stored in the
24-bit APENERGYA and APENERGYB registers is 0x7FFFFF
before the register overflows. The integration time under these
conditions can be calculated as follows:
Time = 0x7FFFFF × 4.76 μs = 39.9 sec
0
23
APENERGYx
0
(28)