ade7953 Analog Devices, Inc., ade7953 Datasheet
ade7953
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ade7953 Summary of contents
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... Two on-chip integrators facilitate the use of Rogowski coil sensors. The ADE7953 provides access to on-chip meter registers via a variety of communication interfaces including SPI, I UART. Two configurable low jitter pulse output pins provide outputs that are proportional to active, reactive, or apparent energy, as well as current and voltage rms ...
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... Alternative Output Functions ....................................................... 48 ADE7953 Interrupts ....................................................................... 49 Primary Interrupts (Voltage Channel and Current Channel A) .................................................................................. 49 Current Channel B Interrupts .................................................. 49 Communicating with the ADE7953 ............................................ 50 Communication Autodetection ............................................... 50 Locking the Communication Interface ................................... 50 SPI Interface ................................................................................ 51 Interface ................................................................................ 52 UART Interface ........................................................................... 54 Rev Page ...
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... Communication Verification and Security .................................. 56 Write Protection .......................................................................... 56 Communication Verification ..................................................... 56 Checksum Register ..................................................................... 57 REVISION HISTORY 2/11—Revision 0: Initial Version ADE7953 Registers ......................................................................... 58 ADE7953 Register Descriptions ............................................... 60 Outline Dimensions ........................................................................ 65 Ordering Guide ........................................................................... 65 Rev Page ADE7953 ...
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... ADE7953 SPECIFICATIONS VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.58 MHz, T Table 1. Parameter PHASE ERROR BETWEEN CHANNELS Power Factor = 0.8 Capacitive Power Factor = 0.5 Inductive ACTIVE ENERGY MEASUREMENT Active Energy Measurement Error (Current Channel A) Active Energy Measurement Error (Current Channel B) AC Power Supply Rejection ...
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... V 0.4 V 3.0 V 3.6 V 6.8 mA Rev Page ADE7953 Test Conditions/Comments CF1 or CF2 frequency > 6.25 Hz CF1 or CF2 frequency < 6.25 Hz CF1 or CF2 frequency = 500 μA at 25°C SOURCE 25°C SINK Nominal 1 REF pin T = 25°C A All specifications CLKIN = 3.58 MHz VDD = 3.3 V ± ...
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... ADE7953 TIMING CHARACTERISTICS SPI Interface Timing VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.58 MHz, T Table 2. Parameter Description SCLK edge CS t SCLK period SCLK t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge ...
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... MIN MAX Fast Mode Max Min Max 100 0 400 0.6 1.3 0.6 0.6 3.45 0 0.9 100 1000 20 300 300 20 300 0.6 1 BUF SU;STO STOP START CONDITION CONDITION ADE7953 Unit kHz μs μs μs μs μ μs μs ns ...
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... ADE7953 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 4. Parameter Rating VDD to AGND −0 +3.7 V VDD to DGND −0 +3.7 V Analog Input Voltage to AGND, − IAP, IAN, IBP, IBN, VP, VN Reference Input Voltage to AGND −0 VDD + 0.3 V Digital Input Voltage to DGND − ...
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... ADE7953. The clock frequency for specified operation is 3.58 MHz. Ceramic load capacitors of a few tens of picofarads should be used with the gate oscillator circuit. Refer to the crystal manufacturer’s data sheet for the load capacitance requirements. 19 CLKOUT A crystal can be connected across this pin and CLKIN to provide a clock source for the ADE7953 RESET 2 ...
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... Current Channel Zero-Crossing Output Pin. See the Current Channel Zero Crossing section. This pin can be configured to output a range of alternative power quality signals (see the Alternative Output Functions section). 22 IRQ Interrupt Output. See the ADE7953 Interrupts section. 23 CF1 Calibration Frequency Output 1. 24 CF2 Calibration Frequency Output 2 ...
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... Figure 10. Current Channel A Active Energy Error as a Percentage of Reading (Gain = 22, Temperature = 25°C) over Frequency and Power Factor Rev Page ADE7953 PF = –0 +0 +1.0 0.001 0.01 0.1 CURRENT CHANNE L (% FULL SCALE) Integrator Off VDD = 3.30V VDD = 2.97V VDD = 3.63V ...
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... ADE7953 1.0 0.8 –40°C 0.6 +25°C +85°C 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0.0001 0.001 0.01 CURRENT CHANNE L (% FULL SCALE) Figure 11. Current Channel A Reactive Energy Error as a Percentage of Reading (Gain = 1, Power Factor = 0) over Temperature with Internal Reference, Integrator Off 1.0 0 –0.866 0 +0.866 0.4 0.2 0 –0.2 –0.4 – ...
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... FREQUENCY (Hz) with Internal Reference, Integrator Off 1.0 0.8 –40°C 0.6 +25°C +85°C 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0.001 0.01 0.1 CURRENT CHANNE L (% FULL SCALE) Integrator Off 1.0 0 –0.866 0 +0.866 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0.001 0.01 0.1 CURRENT CHANNE L (% FULL SCALE) Integrator Off ADE7953 ...
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... ADE7953 1.0 0 –0.866 +0.866 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 – 1 FREQUENCY (Hz) Figure 23. Current Channel B Reactive Energy Error as a Percentage of Reading (Gain = 1, Temperature = 25°C) over Frequency and Power Factor with Internal Reference, Integrator Off 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0.001 0.01 CURRENT CHANNE L (% FULL SCALE) Figure 24. Current Channel B IRMS Error as a Percentage of Reading (Gain = 1, Temperature = 25° ...
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... +0.866 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0.001 0.01 0.1 CURRENT CHANNE L (% FULL SCALE) Integrator On 1.0 CHANNEL A 0.8 CHANNEL B 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0.001 0.01 0.1 CURRENT CHANNE L (% FULL SCALE) Figure 34. IRMS Error as a Percentage of Reading (Gain = 16, Temperature = 25°C) with Internal Reference, Integrator On ADE7953 ...
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... RESET 2 REVP IAP 5 ZX_I IAN 6 MOSI/SCL/Rx IBP 9 MISO/SDA/Tx IBN 10 SCLK ADE7953 CF2 CF1 33nF VN 11 IRQ 12 VP REF 33nF 3.3V PULL_HIGH 7 CLKOUT PULL_HIGH 8 CLKIN 14 PULL_LOW 4 16 Figure 35. Test Circuit Rev Page 0.1µ ...
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... Gain Error The gain error in the ADCs of the ADE7953 is defined as the per-channel difference between the measured ADC output code (minus the offset) and the ideal output code (see the Current Channel ADCs section and the Voltage Channel ADC section) ...
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... VP is ±500 mV with respect to VN. A common-mode voltage of less than ± recommended. Common-mode voltages in excess of this recommended value may limit the dynamic range capabilities of the ADE7953. A PGA gain stage is provided on the voltage channel with gain options and 16 (see Table 6). ...
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... Oversampling means that the signal is sampled at a rate (frequency) that is many times higher than the bandwidth of interest. For example, the sampling rate in the ADE7953 is 895 kHz, and the bandwidth of interest 1.23 kHz. Oversampling has the effect of spreading the quantization noise (noise due to sampling) over a wider bandwidth ...
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... The current signal must be recovered from the di/dt signal before it can be used. An integrator is therefore necessary to restore the signal to its original form. The ADE7953 has a built-in digital integrator on each current channel that recovers the current signal from the di/dt sensor. Both digital integrators are disabled by default. The digital integrator on Current Channel A is enabled by setting the INTENA bit (Bit 0) in the CONFIG register (Address 0x102) ...
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... The reference drift is typically minimal and is usually much smaller than the drift of other components in the meter. By default, the ADE7953 is configured to use the internal reference. If Bit 0 of the EX_REF register (Address 0x800) is set external voltage reference can be applied to the REF pin. ...
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... This helps to stabilize reading-to-reading variation (2) by removing the effect of any 2ω ripple present on the rms measurement. VOLTAGE CHANNEL RMS CALCULATION The ADE7953 provides an rms measurement on the voltage channel. Figure 43 shows the signal path for this calculation. VOLTAGE SIGNAL FROM HPF As shown in Figure 43, the voltage channel ADC output samples are used to continually compute the rms ...
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... Instantaneous Powers and Waveform Sampling section). SIGN OF ACTIVE POWER CALCULATION The active power measurement in the ADE7953 is a signed calcu- lation. If the phase differential between the current and voltage waveforms is more than 90°, the power is negative. Negative INSTANTANEOUS power indicates that energy is being injected back into the grid ...
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... T is the sample period. The discrete time sample period (T) for the accumulation registers in the ADE7953 is 4.76 μs (1/210 kHz). This is illustrated in Figure 46, which shows the energy register roll-over rates with full-scale inputs. AENERGYx[23:0] 0x7FFFFF 0x3FFFFF ...
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... The accumulation time should be written to the LINECYC register (Address 0x101) in the unit of number of half line cycles. The ADE7953 can accumulate energy for up to 65,535 half line cycles. This equates to an accumulation period of approximately 655 sec with 50 Hz inputs and 546 sec with 60 Hz inputs ...
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... After the first line cycle accumulation is complete, all successive readings will be correct. ACTIVE ENERGY ACCUMULATION MODES Signed Accumulation Mode The default active energy accumulation mode for the ADE7953 is a signed accumulation based on the active power information. Positive-Only Accumulation Mode The ADE7953 includes a positive-only accumulation mode option for Current Channel A and Current Channel B active energy ...
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... Instantaneous Powers and Waveform Sampling section). (21) SIGN OF REACTIVE POWER CALCULATION The reactive power measurement in the ADE7953 is a signed calculation. If the current waveform is leading the voltage wave- form, the reactive power is negative. Negative reactive power indicates a capacitive load. If the current waveform is lagging the voltage waveform, the reactive power is positive ...
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... This feature can be disabled by clearing Bit 6 (RSTREAD) of the LCYCMODE register (Address 0x004). The ADE7953 includes two sets of interrupts that are triggered when the reactive energy register is half full (positive or negative) or when an overflow or underflow condition occurs. The first set ...
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... After the first line cycle accumulation is complete, all successive readings will be correct. REACTIVE ENERGY ACCUMULATION MODES Signed Accumulation Mode The default reactive energy accumulation mode for the ADE7953 is a signed accumulation based on the reactive power information. Antitamper Accumulation Mode The ADE7953 includes an antitamper accumulation mode that accumulates reactive energy depending on the sign of the active power ...
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... Bit 6 (RSTREAD) of the LCYCMODE register (26) (Address 0x004). The ADE7953 includes two sets of interrupts that are triggered when the apparent energy register is half full (positive or negative) or when an overflow or underflow condition occurs. The first set of interrupts is associated with the Current Channel A apparent energy, and the second set of interrupts is associated with the Current Channel B apparent energy ...
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... ADC Apparent Energy Line Cycle Accumulation Mode In apparent energy line cycle accumulation mode, the energy accumulation of the ADE7953 is synchronized to the voltage channel zero crossing so that the apparent energy on Current Channel A and Current Channel B can be accumulated over an integral number of half line cycles. Line cycle accumulation ...
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... The pulse outputs are active low. The maximum output frequency with ac inputs at full scale and with CFxDEN = 0x00 is approxi- mately 210 kHz. The ADE7953 includes two unsigned 16-bit registers, CF1DEN (Address 0x103) and CF2DEN (Address 0x104) that control the CF output frequency on the CF1 and CF2 pins, respectively. The ...
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... Address 0x380) provide the calibration adjustment and function in the same way as the BIGAIN register. PHASE CALIBRATION (29) The ADE7953 is designed to function with a variety of current transducers, including those that induce inherent phase errors. A phase error of 0.1° to 0.3° is not uncommon for a current transformer (CT). These phase errors can vary from part to part, and they must be corrected to achieve accurate power readings ...
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... The ADE7953 includes offset calibration registers for the active, reactive, and apparent powers on Current Channel A and Current Channel B. Offsets can exist in the power calculations due to crosstalk between channels on the PCB and in the ADE7953. The offset calibration allows these offsets to be removed to increase the accuracy of the measurement at low input levels. ...
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... PERIOD MEASUREMENT The ADE7953 provides a period measurement of the voltage channel. This measurement is provided in the 16-bit, unsigned period register (Address 0x10E). The period register is updated once every line period and has a settling time associated with it before the period measurement is stable. ...
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... IRQ pin by setting the WSMP bit (Bit 17) in the IRQENA register (Address 0x22C and Address 0x32C). The ADE7953 also provides the option of issuing an unlatched, data-ready signal at the same rate of 6.99 kHz. This signal provides the same information as the WSMP interrupt, but it is unlatched and, therefore, does not need to be serviced each time that new data is available ...
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... USING THE LINE CYCLE ACCUMULATION MODE TO DETERMINE THE POWER FACTOR If a power factor measurement with more averaging is required, the ADE7953 can use the line cycle accumulation measurement on the active and apparent energies to determine the power factor (see the Active Energy Line Cycle Accumulation Mode section and the Apparent Energy Line Cycle Accumulation Mode section) ...
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... ADE7953 ANGLE MEASUREMENT The ADE7953 can measure the time delay between the current and voltage inputs. This feature is available on both Current Channel A and Current Channel B. The negative-to-positive transitions identified by the zero-crossing detection circuit are used as a start and stop for the measurement (see Figure 60). ...
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... The ADE7953 warns of this condition and stops energy accumula- tion if the energy falls below a programmable threshold. The ADE7953 includes a no-load feature on the active, reactive, and apparent energy measurements. This allows a true no-load condition to be detected and also prevents creep in purely resistive, inductive, or capacitive load conditions ...
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... ADE7953 Active Energy No-Load Status Bits In addition to the active energy no-load interrupt, the ADE7953 includes two unlatched status bits that continually monitor the no-load status of Current Channel A and Current Channel B. The ACTNLOAD_A and ACTNLOAD_B bits are located in the ACCMODE register (Address 0x201 and Address 0x301). These bits differ from the interrupt status bits in that they are unlatched and can, therefore, be used to drive an LED ...
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... Channel B triggers the IRQ alternative output (see the Channel B Interrupts section). Apparent Energy No-Load Status Bits In addition to the apparent energy no-load interrupt, the ADE7953 includes two unlatched status bits that continually monitor the no-load status of Current Channel A and Current Channel B. Current The VANLOAD_A and VANLOAD_B bits are located in the ACCMODE register (Address 0x201 and Address 0x301) ...
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... ZXIB bit (Bit 12) of the IRQSTATB register (Address 0x230 and Address 0x330) is set to 1. Figure 63 shows the operation of the voltage channel zero-crossing interrupt shown by the dotted line in Figure 63, the ADE7953 can be configured to trigger a zero-crossing event on only the positive- ZX going or the negative-going zero crossing. The ZX_EDGE bits (Bits[13:12]) of the CONFIG register (Address 0x102) set the edge that triggers the zero-crossing event ...
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... To prevent spurious zero crossings when a very small input is present, an internal threshold is included on all channels of the ADE7953. This fixed threshold is set to a range of 1250:1 of the input full scale. If any input signal falls below this level, no zero- crossing signals are produced by the ADE7953 because they can be assumed to be noise ...
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... ADE7953 VOLTAGE SAG DETECTION The ADE7953 includes a sag detection feature that warns the user when the absolute value of the line voltage falls below the programmable threshold for a programmable number of line cycles. This feature can provide an early warning signal that the line voltage is dropping out. The voltage sag feature is controlled by two registers: SAGCYC (Address 0x000) and SAGLVL (Address 0x200 and Address 0x300) ...
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... PEAK DETECTION The ADE7953 includes a peak detection feature on both Current Channel A (phase) and Current Channel B (neutral) and on the voltage channel. This feature continuously records the maximum value of the voltage and current waveforms. Peak detection can be used with overvoltage and overcurrent detection to provide a complete swell detection function (see the Overcurrent and Overvoltage Detection section) ...
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... These bits are enabled by default and are disabled in the corresponding no-load condition. In addition to the sign indication bits, the ADE7953 also includes four sign indication interrupts. If enabled, these interrupts cause the IRQ pin to go low when the polarity of the power changes. ...
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... OVLVL OV (BIT 16) OF IRQSTATA REGISTER Figure 66. Overvoltage Detection As shown in Figure 66, if the ADE7953 detects an overvoltage condition, the OV bit (Bit 16) of the IRQSTATA register (Address 0x22D and Address 0x32D) is set to 1. This bit can be cleared by reading the RSTIRQSTATA register (Address 0x22E and Address 0x32E). The overcurrent detection feature works in a similar manner (see Figure 67) ...
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... ADE7953 ALTERNATIVE OUTPUT FUNCTIONS The ADE7953 includes three output pins that are configured by default to output power quality information. • Pin 1 (ZX) provides a voltage channel zero-crossing signal, as described in the Voltage Channel Zero Crossing section. • Pin 21 (ZX_I) provides a current channel zero-crossing signal, as described in the Current Channel Zero Crossing section. • ...
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... RESET interrupt that is located within the group of primary interrupts. This interrupt is enabled by default and signals the end of a software or hardware reset. On power-up, this interrupt is triggered to signal that the ADE7953 is ready to receive communication from the microcontroller. This interrupt should be serviced as described in the Primary Interrupts (Voltage Channel and Current Channel A) section prior to configuring the ADE7953 ...
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... ADE7953 COMMUNICATING WITH THE ADE7953 All ADE7953 features can be accessed via a group of on-chip registers. For a detailed list of all the registers, see the ADE7953 Registers section. Three different communication interfaces can be used to access the on-chip registers. • 4-pin SPI interface • 2 2-pin bidirectional I C interface • ...
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... When the third byte transmission is complete, the register data is either sent from the ADE7953 on the MISO pin (in the case of a read written to the ADE7953 MOSI pin by the external microcontroller (in the case of a write). All data is sent or received MSB first. The length of the data transfer depends on the width of the register being accessed ...
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... This consists of the master transmitting a single byte containing the address of the slave device and the nature of the operation (read or write). The address of the ADE7953 is 0111000X. Bit 7 in the address byte indicates whether a read or a write is required: 0 indicates a write, and 1 indicates a read. The communication continues as described in the following sections until the master issues a stop condition and the bus returns to the idle condition ...
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... Because this first step sets up the pointer to the address, the LSB of the start byte should be set to 0 (write). The start condition is followed by the 16-bit address of the target register. After each byte is received, the ADE7953 issues an acknowledge (ACK) to the master. 15 ...
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... The UART interface operates at a fixed baud rate of 4800 bps and is therefore suitable for low speed designs. The UART interface on the ADE7953 is accessed via the Tx pin (Pin 26), which transmits data from the ADE7953, and the Rx pin (Pin 27), which receives data from the microcontroller. A simple master/slave topology is implemented on the UART inter- face with the ADE7953 acting as the slave ...
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... When the read packet is decoded, the ADE7953 sends the data from the selected register out on the Tx pin (see F4 and F5 in Figure 73). This occurs approximately 0.1 ms after the complete frame is received. This data can bytes long, depending on the size of the register that is being accessed ...
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... SPI UART interface is ignored. Resetting the WRITE_ PROTECT bits to 0 reinstates full access to the register banks. COMMUNICATION VERIFICATION The ADE7953 includes a set of three registers that allow any 2 communication via SPI, I LAST_OP (Address 0x0FD), LAST_ADD (Address 0x1FE), and LAST_RWDATA registers record the type, address, and data of the last successful communication, respectively ...
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... ADE7953 has changed. The recommended response is to issue a hardware/software reset, which resets all ADE7953 registers, including reserved registers, to their default values. The ADE7953 should then be reconfigured with the design-specific settings. An interrupt associated with the checksum feature can provide an external warning signal on the IRQ pin if the CRC register value changes after initial configuration ...
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... ADE7953 REGISTERS The ADE7953 contains registers that are 8, 16, 24, and 32 bits long. All signed registers are in the twos complement format with the exception of the PHCALA and PHCALB registers, which are in sign magnitude format. The 24-bit and 32-bit registers contain the same data but can be accessed in two different register lengths. The 24-bit register option increases communication speed ...
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... IRMS offset (Current Channel A) R/W 0x000000 Signed Voltage channel offset R/W 0x000000 Signed VRMS offset R/W 0x000000 Signed Active power offset correction (Current Channel A) R/W 0x000000 Signed Reactive power offset correction (Current Channel A) R/W 0x000000 Signed Apparent power offset correction (Current Channel A) Rev Page ADE7953 ...
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... BIOS 0x292 0x392 BIRMSOS 0x295 0x395 BWATTOS 0x296 0x396 BVAROS 0x297 0x397 BVAOS 0x2FF 0x3FF LAST_RWDATA ADE7953 REGISTER DESCRIPTIONS Table 16. DISNOLOAD Register (Address 0x001) Bits Bit Name Default 0 DIS_APNLOAD 0 1 DIS_VARNLOAD 0 2 DIS_VANLOAD 0 Table 17. LCYCMODE Register (Address 0x004) Bits Bit Name ...
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... CF2 is proportional to IRMS (Current Channel B) 1000 CF2 is proportional to IRMS (Current Channel A) + IRMS (Current Channel B) 1001 CF2 is proportional to active power (Current Channel A) + active power (Current Channel CF1 output is enabled 1 = CF1 output is disabled 0 = CF2 output is enabled 1 = CF2 output is disabled Rev Page ADE7953 ...
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... ADE7953 Table 20. ALT_OUTPUT Register (Address 0x110) Bits Bit Name Default [3:0] ZX_ALT 0000 [7:4] ZXI_ALT 0000 [11:8] REVP_ALT 0000 Description Configuration of ZX pin (Pin 1) Setting ZX Pin Configuration 0000 ZX detection is output on Pin 1 (default) 0001 Sag detection is output on Pin 1 0010 Reserved 0011 Reserved 0100 Reserved 0101 ...
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... Current Channel B active energy is out of no-load condition 1 = Current Channel B active energy is in no-load condition 0 = Current Channel B apparent energy is out of no-load condition 1 = Current Channel B apparent energy is in no-load condition 0 = Current Channel B reactive energy is out of no-load condition 1 = Current Channel B reactive energy is in no-load condition Rev Page ADE7953 ...
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... ADE7953 Interrupt Enable and Interrupt Status Registers Current Channel A and Voltage Channel Registers Table 22. IRQENA Register (Address 0x22C and Address 0x32C), IRQSTATA Register (Address 0x22D and Address 0x32D), and RSTIRQSTATA Register (Address 0x22E and Address 0x32E) Bits Bit Name Description 0 AEHFA ...
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... Dimensions shown in millimeters Package Description 28-Lead LFCSP_WQ 28-Lead LFCSP_WQ, 13” Tape and Reel Evaluation Board Rev Page 3.40 3. FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Package Option CP-28-6 CP-28-6 ADE7953 ...
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... ADE7953 NOTES Rev Page ...
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... NOTES Rev Page ADE7953 ...
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... ADE7953 NOTES refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09320-0-2/11(0) Rev Page ...