xe88lc05 ETC-unknow, xe88lc05 Datasheet - Page 35

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xe88lc05

Manufacturer Part Number
xe88lc05
Description
16 10 Bit Data Acquisition Ultra Low-power Microcontroller
Manufacturer
ETC-unknow
Datasheet

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Table 9.3:
Note:
9.6 The DAC of signal DAC
Note:
Table 9.4:
35
DAC signal amplifier performances
1) For the minimal resistive load and the maximal capacitive load
2) At DC
3) Short circuit protection at ~5mA.
4) GBW when the maximal load is cl0 and with the bit BW=0
5) GBW when the maximal load is cl1 and with the bit BW=1
6) In both cases BW=0 and BW=1 for the maximal capacitive load and the minimal resistive
load.
7) For maximal load cl0, BW=0 and maximal resistive load rl
The DAC of signal DAC can be used as a regular PWM DAC (NSorder set to 00), or a sigma-
delta DAC (first or second order). The most efficient setting is the second order sigma-delta
(NSorder set to 10), and this is the mode that we describe below. In order to function according
to the following computation, it must be followed by a second order filter or larger with a given
cut-off frequency.
The DAC output is ratiometric to power supply. It is highly important to avoid parasitic on power
supply. It is recommended to have no heavy switching on output ports for precise DAC output.
The D/A resolution in bits is given by (second order filter):
with:
m = PWM resolution in bits (4 .. 11)
PWM resolution setting
NSorder = order of the noise shaper = (0 .. 2)
CMRR
resolution bit
noise
sym
ibias
voff
ioff
code_lmax
000
001
010
011
100
101
110
111
common mode rejection
quiescent bias current
(
integrated input noise
description
)
off current
=
offset
0.226
Data Acquisition Microcontroller
+
(PWM resolution in bits)
m
+
(
NSorder
min
60
10
11
m
4
5
6
7
8
9
200
typ
(
q 2.65
max
100
500
±5
1
)
)
uVrms
unit
mV
dB
uA
uA
Comments
XE88LC05
2
D0109-40

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