cy8c5246pvi-092 Cypress Semiconductor Corporation., cy8c5246pvi-092 Datasheet - Page 5

• Manufacturer Part Number: cy8c5246pvi-092
• Description: Programmable System-on-chip Psoc
• Manufacturer: Cypress Semiconductor Corporation.

clocks, together with programmable clock dividers, provide the
flexibility to integrate most timing requirements.
The CY8C52 family supports a wide supply operating range from
1.71 to 5.5V. This allows operation from regulated supplies such
as 1.8 ± 5%, 2.5V ±10%, 3.3V ± 10%, or 5.0V ± 10%, or directly
from a wide range of battery types. In addition, it provides an
integrated high efficiency synchronous boost converter that can
power the device from supply voltages as low as 0.5V. This
enables the device to be powered directly from a single battery
or solar cell. In addition, the designer can use the boost converter
to generate other voltages required by the device, such as a 3.3V
supply for LCD glass drive. The boost’s output is available on the
Vboost pin, allowing other devices in the application to be
powered from the PSoC.
PSoC supports a wide range of low power modes. These include
a 300 nA hibernate mode with RAM retention and a 2 µA sleep
mode with real time clock (RTC). In the second mode the
optional 32.768 kHz watch crystal runs continuously and
maintains an accurate RTC.
Power to all major functional blocks, including the programmable
digital and analog peripherals, can be controlled independently
by firmware. This allows low power background processing
when some peripherals are not in use. This, in turn, provides a
total device current of only 2 mA when the CPU is running at
6 MHz.
Document Number: 001-55034 Rev. *A
(TRACEDATA[0], GPIO) P2[4]
(TRACEDATA[1], GPIO) P2[5]
(TRACEDATA[2], GPIO) P2[6]
(TRACEDATA[3], GPIO) P2[7]
(TRACECLK, GPIO) P2[3]
(Extref0, GPIO) P0[3]
(GPIO) P0[0]
(GPIO) P0[1]
(GPIO) P0[2]
(GPIO) P0[4]
(GPIO) P0[5]
(GPIO) P0[6]
(GPIO) P0[7]
(SIO) P12[2]
(SIO) P12[3]
PRELIMINARY
Figure 2-1. 48-Pin SSOP Part Pinout
Vddio0
Vddio2
Vboost
Vddd
Vccd
Vssd
Vssb
Vbat
Ind
10
11
12
13
15
17
18
19
20
21
22
23
24
14
16
1
2
3
4
5
6
7
8
9
Lines show
Vddio to I/O
supply
association
SSOP
The details of the PSoC power modes are covered in the
System”
PSoC uses JTAG (4 wire) or Serial Wire Debug (SWD) (2 wire)
interfaces for programming, debug, and test. Using these
standard interfaces enables the designer to debug or program
the PSoC with a variety of hardware solutions from Cypress or
third party vendors. The Cortex-M3 debug and trace modules
include Flash Patch and Breakpoint (FPB), Data Watchpoint and
Trace (DWT), Embedded Trace Macrocell (ETM), and Instru-
mentation Trace Macrocell (ITM). These modules have many
features to help solve difficult debug and trace problems. Details
of the programming, test, and debugging interfaces are
discussed in the
section on page 51 of this data sheet.
2. Pinouts
The Vddio pin that supplies a particular set of pins is indicated
by the black lines drawn on the pinout diagrams in
through
support multiple interface voltage levels, eliminating the need for
off-chip level shifters. Each Vddio may sink up to 100 mA total to
its associated I/O pins. On the 68 pin and 100 pin devices each
set of Vddio associated pins may sink up to 100 mA. The 48 pin
device may sink up to 100 mA total for all Vddio0 plus Vddio2
associated I/O pins and 100 mA total for all Vddio1 plus Vddio3
associated I/O pins.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
PSoC
Vdda
Vssa
Vcca
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, I2C1: SCL)
Vddio3
P15[1] (GPIO, MHz XTAL: Xi)
P15[0] (GPIO, MHz XTAL: Xo)
Vccd
Vssd
Vddd
P15[7] (USBIO, D-, SWDCK)
P15[6] (USBIO, D+, SWDIO)
P1[7] (GPIO)
P1[6] (GPIO)
Vddio1
P1[5] (GPIO, nTRST)
P1[4] (GPIO, TDI)
P1[3] (GPIO, TDO, SWV)
P1[2] (GPIO, configurable XRES)
P1[1] (GPIO, TCK, SWDCK)
P1[0] (GPIO, TMS, SWDIO)
Figure
section on page 22 of this data sheet.
®
2-3. Using the Vddio pins, a single PSoC can
5: CY8C52 Family Data Sheet
[2]
“Programming, Debug Interfaces, Resources”
[2]
[2]
Figure 2-1
Page 5 of 85
“Power
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