cy8c5246pvi-092 Cypress Semiconductor Corporation., cy8c5246pvi-092 Datasheet - Page 23

• Manufacturer Part Number: cy8c5246pvi-092
• Description: Programmable System-on-chip Psoc
• Manufacturer: Cypress Semiconductor Corporation.

Table 6-2. Power Modes
Table 6-3. Power Modes Wakeup Time and Power Consumption
Figure 6-3. Power Mode Transitions
6.2.1.1 Active Mode
Document Number: 001-55034 Rev. *A
Note
Active
Alternate
Active
Sleep
Hibernate
Power Modes
Active
Alternate
Active
Sleep
Hibernate <100 µs
5. IMO 6 MHz, CPU 6 MHz, all peripherals disabled.
Modes
Sleep
Alternate
Active
<12 µs
Wakeup
-
-
Time
Primary mode of operation, all
peripherals available (program-
mable)
Similar to Active mode, and is
typically configured to have
fewer peripherals active to
reduce power. One possible
configuration is to turn off the
CPU and Flash, and run periph-
erals at full speed
All subsystems automatically
disabled
All subsystems automatically
disabled
Lowest power consuming mode
with all peripherals and internal
regulators disabled, except
hibernate regulator is enabled
Configuration and memory
contents retained
2 mA
20 µA
2 µA
300 nA
Power
(Typ)
Description
[5]
Active
Sleep
Yes
User
defined
No
No
Execution
Code
PRELIMINARY
All
All
I
None
Resources
2
C
Wakeup, reset,
manual register
entry
Manual register
entry
Manual register
entry
Manual register
entry
Entry Condition Wakeup Source
Digital
Hibernate
All
All
Comparator ILO/kHzECO
None
Resources
Analog
Any interrupt
Any interrupt
PICU,
comparator, I
RTC, CTW,
XRES_N, WDR,
PPOR, HBR
PICU, XRES_N,
HBR
Active mode is the primary operating mode of the device. When
in active mode, the active configuration template bits control
which available resources are enabled or disabled. When a
resource is disabled, the digital clocks are gated, analog bias
currents are disabled, and leakage currents are reduced as
appropriate. User firmware can dynamically control subsystem
power by setting and clearing bits in the active configuration
template. The CPU can disable itself, in which case the CPU is
automatically reenabled at the next wakeup event.
When a wakeup event occurs, the global mode is always
returned to active, and the CPU is automatically enabled,
regardless of its template settings. Active mode is the default
global power mode upon boot.
PSoC
All
All
None
Clock Sources
Available
2
®
C,
5: CY8C52 Family Data Sheet
Any (program-
mable)
Any (program-
mable)
ILO/ECO32K
Active Clocks
-
-
PICU, comparator,
I
PICU
Wakeup Sources Reset Sources
2
C, RTC, CTW
All regulators available.
Digital and analog
regulators can be disabled
if external regulation used.
All regulators available.
Digital and analog
regulators can be disabled
if external regulation used.
Both digital and analog
regulators buzzed.
Digital and analog
regulators can be disabled
if external regulation used.
Only hibernate regulator
active.
Regulator
All
All
XRES, LVD,
WDR
XRES, HRES
Page 23 of 85
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