xc6vlx760 Xilinx Corp., xc6vlx760 Datasheet - Page 2

• Manufacturer Part Number: xc6vlx760
• Description: Fpga
• Manufacturer: Xilinx Corp.

Virtex-6 Family Overview
Virtex-6 FPGA Feature Summary
Table 1: Virtex-6 FPGA Feature Summary by Device
Virtex-6 FPGA Device-Package Combinations and Maximum I/Os
Virtex-6 FPGA package combinations with the maximum available I/Os per package are shown in
Table 2: Virtex-6 FPGA Device-Package Combinations and Maximum Available I/Os
2
Notes:
1.
2.
3.
4.
5.
6.
7.
Notes:
1.
XC6VLX75T
XC6VLX130T
XC6VLX195T
XC6VLX240T
XC6VLX365T
XC6VLX550T
XC6VLX760
XC6VSX315T
XC6VSX475T
Device
XC6VLX75T
XC6VLX130T
XC6VLX195T
XC6VLX240T
XC6VLX365T
XC6VLX550T
XC6VLX760
XC6VSX315T
XC6VSX475T
Device
Each Virtex-6 FPGA slice contains four LUTs and eight flip-flops, only some slices can use their LUTs as distributed RAM or SRLs.
Each DSP48E1 slice contains a 25 x 18 multiplier, an adder, and an accumulator.
Block RAMs are fundamentally 36 Kbits in size. Each block can also be used as two independent 18 Kb blocks.
Each CMT contains two mixed-mode clock managers (MMCM).
This table lists individual Ethernet MACs per device.
Does not include configuration Bank 0.
This number does not include RocketIO GTX transceivers.
Flip-chip packages are also available in Pb-Free versions (FFG).
Size (mm)
Package
128,000
199,680
241,152
364,032
549,888
758,784 118,560
314,880
476,160
74,496
Logic
Cells
8 GTXs
8 GTXs
GTs
FFG484
Slices
23 x 23
11,640
20,000
31,200
37,680
56,880
85,920
49,200
74,400
FF484
Configurable Logic
Blocks (CLBs)
(1)
240
240
Distributed
I/O
RAM (Kb)
5,090
7,640
1,045
1,740
3,040
3,650
4,130
6,200
8,280
Max
12 GTXs
12 GTXs
12 GTXs
12 GTXs
DSP48E1
Slices
GTs
1,344
2,016
288
480
640
768
576
864
864
FFG784
29 x 29
FF784
(2)
18 Kb
1,264
1,440
1,408
2,128
312
528
688
832
832
Block RAM Blocks
360
400
400
400
I/O
(3)
www.xilinx.com
1,064
36 Kb
156
264
344
416
416
632
720
704
20 GTXs
20 GTXs
20 GTXs
20 GTXs
Max (Kb)
12,384
14,976
14,976
22,752
25,920
25,344
38,304
GTs
5,616
9,504
FFG1156
FF1156
35 x 35
MMCMs
10
10
12
12
18
18
12
18
6
600
600
600
600
I/O
(4)
PCI Express
Blocks for
Interface
24 GTXs
24 GTXs
36 GTXs
24 GTXs
36 GTXs
1
2
2
2
2
2
0
2
2
GTs
42.5 x 42.5
FFG1759
FF1759
Ethernet
MACs
Advance Product Specification
4
4
4
4
4
4
0
4
4
DS150 (v1.0) February 2, 2009
(5)
720
720
840
720
840
I/O
Table
Transceivers
Maximum
GTX
12
20
20
24
24
36
24
36
0
2.
0 GTXs
0 GTXs
GTs
42.5 x 42.5
FFG1760
FF1760
Banks
Total
I/O
15
15
18
18
30
30
18
21
9
(6)
1200
1200
I/O
1200
1200
I/O
User
Max
360
600
600
720
720
720
840
(7)
R