xc6vlx760 Xilinx Corp., xc6vlx760 Datasheet

xc6vlx760

Manufacturer Part Number

xc6vlx760

Description

Fpga

Manufacturer

Xilinx Corp.

Datasheet

1.XC6VLX760.pdf (8 pages)

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DS150 (v1.0) February 2, 2009

General Description

The Virtex®-6 family provides the newest, most advanced features in the FPGA market. Using the third generation ASMBL™ (Advanced

Silicon Modular Block) column-based architecture, the Virtex-6 family contains multiple distinct platforms (sub-families). This overview

covers the devices in the LXT and SXT platforms. Each platform contains a different ratio of features to address the needs of a wide variety

of advanced logic designs. In addition to the high-performance logic fabric, Virtex-6 FPGAs contain many built-in system-level blocks,

including 36 Kb block RAM/FIFOs, third generation DSP48E1 slices, SelectIO™ technology with built-in digitally controlled impedance,

ChipSync™ source-synchronous interface blocks, system monitor functionality, enhanced mixed-mode clock management blocks,

advanced configuration options, power-optimized high-speed serial transceiver blocks, PCI Express® compatible integrated blocks, and

tri-mode Ethernet media access controllers (MACs). These features allow logic designers to build the highest levels of performance and

functionality into their FPGA-based systems. Built on a 40 nm state-of-the-art copper process technology, Virtex-6 FPGAs are a

programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength of FPGAs.

Virtex-6 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP designers,

and high-performance embedded systems designers with unprecedented logic, DSP, connectivity, and soft microprocessor capabilities.

Summary of Virtex-6 FPGA Features

•

All other trademarks are the property of their respective owners.

DS150 (v1.0) February 2, 2009

Advance Product Specification

Two Base Platforms

−

Cross-platform compatibility

−

Advanced, high-performance, FPGA Logic

−

Powerful mixed-mode clock managers (MMCM) clocking

−

36-Kb block RAM/FIFOs

−

High-performance parallel SelectIO technology

−

Virtex-6 LXT Platform: High-performance logic with

advanced serial connectivity

Virtex-6 SXT Platform: Highest signal processing

capability with advanced serial connectivity

More platforms to follow

LXT and SXT devices are footprint compatible in the

same package

Real 6-input look-up table (LUT) technology

Dual LUT5 (5-LUT) option

LUT/dual flip-flop pair for applications requiring rich

Improved routing efficiency

64 bit (or 32 x 2 bit) distributed LUT RAM option

SRL32/dual SRL16 with registered outputs option

MMCM blocks provide zero-delay buffering, frequency

synthesis, clock-phase shifting, input-jitter filtering, and

phase-matched clock division

True dual-port RAM blocks

Programmable

Enhanced programmable FIFO logic

Built-in optional error-correction circuitry

Optionally use each block as two independent 18 Kb

blocks

1.2 to 2.5V I/O operation

Source-synchronous interfacing using

ChipSync™ technology

Digitally controlled impedance (DCI) active termination

Flexible fine-grained I/O banking

High-speed memory interface support with integrated

write-leveling capability

True dual-port widths up to 36 bits

Simple dual-port widths up to 72 bits

www.xilinx.com

•

Advanced DSP48E1 slices

−

Flexible configuration options

−

System Monitor capability on all devices

−

Integrated interface blocks for PCI Express designs

−

RocketIO™ GTX transceivers 150 Mb/s to 6.5 Gb/s

Integrated 10/100/1000 Mb/s Ethernet MAC block

−

40 nm copper CMOS process technology

1.0V core voltage (-1, -2, -3 speed grades only)

Lower-power 0.9V core voltage (-1L speed grade only)

High signal-integrity flip-chip packaging available in standard

or Pb-free package options

25 x 18, two's complement multiplier/accumulator

Optional pipelining

New optional pre-adder to assist filtering applications

Optional bitwise logic functionality

Dedicated cascade connections

SPI and Parallel Flash interface

Multi-bitstream support with dedicated fallback

reconfiguration logic

Automatic bus width detection

On-chip/off-chip thermal and supply voltage monitoring

JTAG access to all monitored quantities

Designed to the PCI Express Base Specification 2.0

Gen1 (2.5 Gb/s) and Gen2 (5 Gb/s) support with GTX

transceivers

Endpoint and Root Port capable

x1, x2, x4, or x8 lane support per block

One virtual channel, eight traffic classes

Supported 1000BASE-X PCS/PMA and SGMII using

RocketIO GTX transceivers

Supports MII, GMII, and RGMII using SelectIO

resources

2500Mb/s support available

Virtex-6 Family Overview

Advance Product Specification

Related parts for xc6vlx760

xc6vlx760 Summary of contents

Page 1

R DS150 (v1.0) February 2, 2009 General Description The Virtex®-6 family provides the newest, most advanced features in the FPGA market. Using the third generation ASMBL™ (Advanced Silicon Modular Block) column-based architecture, the Virtex-6 family contains multiple distinct platforms (sub-families). ...

Page 2

... FF484 Package FFG484 Size (mm Device GTs I/O XC6VLX75T 8 GTXs 240 XC6VLX130T 8 GTXs 240 XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX550T XC6VLX760 XC6VSX315T XC6VSX475T Notes: 1. Flip-chip packages are also available in Pb-Free versions (FFG). 2 Block RAM Blocks DSP48E1 MMCMs (2) Slices ( Max (Kb) 288 312 ...

Page 3

R Configuration Virtex-6 FPGAs store their customized configuration in SRAM-type internal latches. The number of configuration bits is between 16 Mb and 160 MB), depending on device size but independent of the specific user-design implementation, unless ...

Page 4

Virtex-6 Family Overview Clock Management Each Virtex-6 FPGA has up to nine clock management tiles (CMTs), each consisting of two mixed-mode clock managers (MMCMs), which are PLL based. Phase-Locked Loop The MMCM can serve as a frequency synthesizer for a ...

Page 5

R Block RAM Every Virtex-6 FPGA has between 156 and 1064 true dual-port block RAMs, each storing 36 Kbits. Each block RAM has two completely independent ports that share nothing but the stored data. Synchronous Operation Each memory access, read ...

Page 6

Virtex-6 Family Overview Input/Output The number of I/O pins varies from 240 to 1200 depending on device and package size. Each I/O pin is configurable and can comply with a large number of standards, using up to 2.5V. The Virtex-6 ...

Page 7

R The System Monitor does not require explicit instantiation in a design. Once the appropriate power supply connections are made, measurement data can be accessed at any time, even pre-configuration or during power down, through the JTAG test access port ...

Page 8

Virtex-6 Family Overview connectivity, and to block RAMs for data buffering. Combined, these elements implement the Physical Layer, Data Link Layer, and Transaction Layer of the PCI Express protocol. Xilinx provides a light-weight (<100 LUT), configurable, ease-of-use LogiCORE™ wrapper that ...

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