xc3s1000-5fgg900i Xilinx Corp., xc3s1000-5fgg900i Datasheet - Page 13

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xc3s1000-5fgg900i

Manufacturer Part Number
xc3s1000-5fgg900i
Description
Spartan-3 Fpga Family
Manufacturer
Xilinx Corp.
Datasheet
DS099-2 (v2.5) December 4, 2009
Product Specification
OTCLK1
OTCLK2
ICLK1
ICLK2
TCE
OCE
REV
ICE
IQ1
IQ2
T1
T2
SR
O1
O2
T
I
R
Note: All IOB signals originating from the FPGA's internal logic have an optional polarity inverter.
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
SR
SR
SR
SR
SR
SR
REV
REV
REV
REV
REV
REV
Q
Q
Q
Q
Q
Q
Figure 5: Simplified IOB Diagram
TFF1
TFF2
OFF1
OFF2
IFF1
IFF2
MUX
DDR
DDR
MUX
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Delay
Fixed
Delay
Fixed
Three-state Path
Output Path
Input Path
Spartan-3 FPGA Family: Functional Description
Program-
Output
mable
Driver
Single-ended Standards
LVCMOS, LVTTL, PCI
Differential Standards
using V REF
DCI
Pull-Up
Down
Pull-
Keeper
Latch
DS099-2_01_112905
ESD
ESD
V
Pin
I/O Pin
from
Adjacent
IOB
V
CCO
REF
I/O
Pin
13

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