xc3s1000-5fgg900i Xilinx Corp., xc3s1000-5fgg900i Datasheet
xc3s1000-5fgg900i
Manufacturer Part Number
xc3s1000-5fgg900i
Description
Spartan-3 Fpga Family
Manufacturer
Xilinx Corp.
Datasheet
1.XC3S1000-5FGG900I.pdf
(217 pages)
DS099 December 4, 2009
This document includes all four modules of the Spartan
Module 1:
Spartan-3 FPGA Family: Introduction
and Ordering Information
DS099-1 (v2.5) December 4, 2009
•
•
•
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•
Module 2:
Spartan-3 FPGA Family: Functional
Description
DS099-2 (v2.5) December 4, 2009
•
•
•
•
•
•
•
IMPORTANT NOTE: Each module has its own Revision History at the end. Use the PDF "Bookmarks" for easy navigation
in this volume.
© 2003–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other coun-
tries. All other trademarks are the property of their respective owners.
DS099 December 4, 2009
Product Specification
Introduction
Features
Architectural Overview
Array Sizes and Resources
User I/O Chart
Ordering Information
Input/Output Blocks (IOBs)
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-
Configurable Logic Blocks (CLBs)
Block RAM
Dedicated Multipliers
Digital Clock Manager (DCM)
Clock Network
Configuration
IOB Overview
SelectIO™ Interface I/O Standards
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www.xilinx.com
®
-3 FPGA data sheet.
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Spartan-3 FPGA Family
Data Sheet
Product Specification
Module 3:
Spartan-3 FPGA Family: DC and
Switching Characteristics
DS099-3 (v2.5) December 4, 2009
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Module 4:
Spartan-3 FPGA Family: Pinout
Descriptions
DS099-4 (v2.5) December 4, 2009
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DC Electrical Characteristics
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Switching Characteristics
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Pin Descriptions
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Package Overview
Pinout Tables
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Absolute Maximum Ratings
Supply Voltage Specifications
Recommended Operating Conditions
DC Characteristics
I/O Timing
Internal Logic Timing
DCM Timing
Configuration and JTAG Timing
Pin Behavior During Configuration
Footprints
1
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