dsp56001a Freescale Semiconductor, Inc, dsp56001a Datasheet - Page 33

• Manufacturer Part Number: dsp56001a
• Description: 24-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
Note:
Num
39 HR/W Low Setup Time Before
40 HR/W Low Hold Time After
41 HR/W High Setup Time to
42 HR/W High Hold Time After
43 HA0-HA2 Setup Time Before
44 HA0-HA2 Hold Time After
45 DMA HACK Assertion to
46 DMA HACK Deassertion to
47 Delay from HEN Deassertion to
48 Delay from HEN Deassertion to
49 Delay from HEN Assertion to
HEN Assertion
HEN Deassertion
HEN Assertion
HEN/HACK Deassertion
HEN Assertion
HEN Deassertion
HREQ Deassertion (See Note 5)
HREQ Assertion (See Notes 5, 6)
HREQ Assertion for RXL Read
(See Notes 5, 6)
HREQ Assertion for TXL Write
(See Notes 5, 6)
HREQDeassertion for RXL
Read, TXL Write (See Notes 5, 6)
1.
2.
3.
4.
5.
6.
7.
•
•
•
Host synchronization delay (t
external asynchronous input signal, determine whether it is high or low, and synchronize it to the
DSP56001 internal clock.
See Host Port Considerations in the section on Design Considerations.
This timing must be adhered to only if two consecutive writes to the TXL are executed without
polling TXDE or HREQ.
This timing must be adhered to only if two consecutive reads from one of these registers are executed
without polling the corresponding status bits or HREQ.
HREQ is pulled up by a 1 k resistor.
Specifications are periodically sampled and not 100% tested.
May decrease to 0 ns for future versions.
Table 2-9 Host I/O Timing (Continued)(27/33 MHz) (Continued)
for DMA RXL Read
for DMA TXL Write
all other cases
Characteristics
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
DSP56001A/D, Rev. 1
HSDL
t
t
t
t
HSDL
HSDL
HSDL
HSDL
T
T
) is the time period required for the DSP56001 to sample any
Min
H
H
0
4
0
4
0
4
4
4
4
4
4
+ T
+ T
+ T
+ T
+ 4
+ 4
C
C
C
C
27 MHz
+
+
+
+
Max
—
—
—
—
—
—
46
—
—
—
—
—
70
t
t
t
t
HSDL
HSDL
HSDL
HSDL
T
T
Min
H
H
0
4
0
4
0
4
4
4
4
4
4
+ T
+ T
+ T
+ T
+ 4
+ 4
C
C
C
C
33 MHz
+
+
+
+
Host I/O (HI) Timing
Max
—
—
—
—
—
—
46
—
—
—
—
—
65
DSP56001A
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-15