dsp56001a Freescale Semiconductor, Inc, dsp56001a Datasheet - Page 11

• Manufacturer Part Number: dsp56001a
• Description: 24-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

BUS CONTROL
MOTOROLA
PS
DS
X/Y
BR
WT
BG
BS
WR
RD
Signal
Name
Output Tri-stated Program Memory Select—PS is asserted low for external program
Output Tri-stated Data Memory Select—DS is asserted low for external data memory
Output Tri-stated X/Y External Memory Select—This output is driven low during external
Output
Output
Output Tri-stated Write Enable—WR is asserted during external memory write cycles. WR
Output Tri-stated Read Enable—RD is asserted during external memory read cycles. RD is
Input/
Input/
Signal
Type
Tri-stated Bus Request/Wait—The bus request input BR allows another device such
Tri-stated Bus Grant/Bus Select—If OMR Bit 7 is clear, this output is asserted to
during
Reset
State
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memory access. PS is tri-stated when the BG or RESET signal is asserted.
access. DS is tri-stated when the BG or RESET signal is asserted.
Y data memory accesses. It is also driven low during external exception
vector fetches when operating in the Development mode. X/Y is tri-stated
when the BG or RESET signal is asserted.
as a processor or DMA controller to become master of the external data
bus D0–D23 and external address bus a0–a15. When operating mode
register (OMR) bit 7 is clear and BR is asserted, the DSP56001A will
always release the external data bus D0–D23, address bus A0–A15, and
bus control signals PS, DS, X/Y, RD, and WR (i.e. Port A), by tri-stating
these pins after execution of the current instruction has been completed.
If OMR bit 7 is set, this pin is an input that allows an external device to
force wait states during an external Port A operation for as long as WT is
asserted.
Note:
acknowledge an external bus request after Port A has been released.
If OMR Bit 7 is set, this signal is bus strobe, and is asserted when the DSP
accesses Port A.
is tri-stated when the BG or RESET signal is asserted.
tri-stated when the BG or RESET signal is asserted.
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Table 1-7 Bus Control Signals
To prevent erroneous operation, pull up the BR/WT signal when
it is not in use.
DSP56001A/D, Rev. 1
Signal Description
Bus Control
DSP56001A
1-5