dsp56854 Freescale Semiconductor, Inc, dsp56854 Datasheet
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... Data Sheet Technical Data 56800E 16-bit Digital Signal Controllers DSP56854 Rev. 6 01/2007 freescale.com ...
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General Description • 120 MIPS at 120MHz • 16K x 16-bit Program SRAM • 16K x 16-bit Data SRAM • 16-bit Boot ROM • Access words of program or 8M data memory • Chip ...
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Part 1 Overview 1.1 56854 Features 1.1.1 Digital Signal Processing Core • Efficient 16-bit engine with dual Harvard architecture • 120 Million Instructions Per Second (MIPS) at 120MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) • • Four ...
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JTAG/Enhanced On-Chip Emulation (EOnCE) for unobtrusive, real-time debugging • Six (6) independent channels of DMA • 8-bit Parallel Host Interface* • Time of Day • GPIO * Each peripheral I/O can be used alternately as a ...
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... Electrical and timing specifications, pin descriptions, Technical Data Sheet and package descriptions DSP56854 Details any chip issues that might be present Errata 6 are required for a complete description of and proper design with Description 56854 Technical Data, Rev. 6 Order Number DSP56800ERM DSP5685xUM DSP56854 DSP56854E Freescale Semiconductor ...
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Data Sheet Conventions This data sheet uses the following conventions: OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. “asserted” A high true (active high) ...
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Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56854 are organized into functional groups, as shown in as illustrated in Figure 2-1. In signals present. Table 2-1 Functional Group Pin Allocations Power ( ...
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Logic Power I/O Power Analog 1 Power External Bus Chip CS0 - CS3 (GPIOA0 - A3) Select HD0 - HD7 (GPIOB0 - B7) HA0 - HA2 (GPIOB8 - B10) HRWB (HRD) (GPIOB11) Host Host HDS (HWR) (GPIOB12) Interface Interface HCS ...
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Part 3 Signals and Package Information All digital inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are enabled by default. Exceptions: 1. When a pin has GPIO functionality, the pull-up may be disabled under software ...
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Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued) Pin No. Signal Name 5 V DDIO 18 V DDIO 41 V DDIO 55 V DDIO 61 V DDIO 72 V DDIO 91 V DDIO 92 V DDIO ...
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Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued) Pin No. Signal Name A10 46 A11 ...
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Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued) Pin No. Signal Name 107 D6 108 D7 109 D8 110 D9 111 D10 122 D11 ...
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Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued) Pin No. Signal Name 77 CS2 GPIOA2 78 CS3 GPIOA3 30 HD0 GPIOB0 31 HD1 GPIOB1 32 HD2 GPIOB2 36 HD3 GPIOB3 37 HD4 GPIOB4 14 Type Output ...
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Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued) Pin No. Signal Name 38 HD5 GPIOB5 39 HD6 GPIOB6 40 HD7 GPIOB7 82 HA0 GPIOB8 83 HA1 GPIOB9 84 HA2 GPIOB10 Freescale Semiconductor Type Input Host Address ...
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Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued) Pin No. Signal Name 85 HRWB HRD GPIOB11 103 HDS HWR GPIOB12 104 HCS GPIOB13 105 HREQ HTRQ GPIOB14 16 Type Input Host Read/Write (HRWB)—When the HI08 is ...
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Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued) Pin No. Signal Name 106 HACK HRRQ GPIOB15 101 TIO0 GPIOG0 99 TIO1 GPIOG1 98 TIO2 GPIOG2 97 TIO3 GPIOG3 20 IRQA 21 IRQB Freescale Semiconductor Type Input ...
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Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued) Pin No. Signal Name 15 MODA GPIOH0 16 MODB GPIOH1 17 MODC GPIOH2 35 RESET 34 RSTO 65 RXD0 GPIOE0 66 TXD0 GPIOE1 94 RXD1 GPIOE2 18 Type ...
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Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued) Pin No. Signal Name 95 TXD1 GPIOE3 116 STD0 GPIOC0 117 SRD0 GPIOC1 118 SCK0 GPIOC2 119 SC00 GPIOC3 120 SC01 GPIOC4 Freescale Semiconductor Type Output(Z) Serial Transmit ...
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Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued) Pin No. Signal Name 121 SC02 GPIOC5 1 MISO GPIOF0 2 MOSI GPIOF1 3 SCK GPIOF2 20 Type Input/Output ESSI Serial Control Pin 2 (SC02)—This pin is used ...
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Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued) Pin No. Signal Name 4 SS GPIOF3 24 XTAL 25 EXTAL 33 CLKO 54 TCK 52 TDI 51 TDO 53 TMS Freescale Semiconductor Type Input SPI Slave Select ...
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Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued) Pin No. Signal Name 50 TRST Type Input Test Reset (TRST)—As an input, a low signal on this pin provides a reset signal to the ...
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Part 4 Specifications 4.1 General Characteristics The 56854 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The term “5-volt tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process technology, to withstand ...
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Table 4-1 Absolute Maximum Ratings Characteristic Supply voltage, core Supply voltage, IO Supply voltage, analog Digital input voltages Analog input voltages (XTAL, EXTAL) Current drain per pin excluding V DD Junction temperature Storage temperature range 1. V must not exceed ...
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Characteristic Thermal resistance junction-to-ambient (estimated) I/O pin power dissipation Power dissipation Maximum allowed See Section 6.1 for more detail Junction Temperature TA = Ambient Temperature 4.2 DC Electrical Characteristics Table 4-4 DC Electrical Characteristics ...
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Table 4-4 DC Electrical Characteristics (Continued) Operating Conditions SSIO SSA Characteristic V supply current (Core logic, memories, peripherals Run 2 Deep Stop 3 Light Stop V supply current (I/O circuity) DDIO 5 ...
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Figure 4-1 Maximum Run I Freescale Semiconductor 1 5 MAC Mode EMI Mode vs. Frequency (see Notes DDTOTAL 56854 Technical Data, Rev Electrical Characteristics 120 100 80 1. and ...
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Supply Voltage Sequencing and Separation Cautions Figure 4-2 shows two situations to avoid in sequencing the V 3.3V 1. Notes rising before DDIO rising much faster than ...
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Regulator Supply Figure 4-3 Example Circuit to Control Supply Sequencing 4.4 AC Electrical Characteristics Timing waveforms in Section 4.2 for all pins except XTAL, which is tested using the input levels in V and V for an input signal ...
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External Clock Operation The 56854 system clock can be derived from a crystal or an external system clock signal. To generate a reference frequency using the internal oscillator, a reference crystal must be connected between the EXTAL and XTAL ...
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Low Speed External Clock Source (2-4MHz) The recommended method of connecting an external clock is given in source is connected to XTAL and the EXTAL pin is held at V set to 0. Figure 4-8 Connecting a Low Speed ...
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Operating Conditions SSIO SSA Characteristic External reference crystal frequency for the PLL PLL output frequency 2 PLL stabilization time 1. An externally supplied reference clock should be as free as possible from any phase ...
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A0-Axx, AWR t WRWR WR t DWR D0-D15 Note: During read-modify-write instructions and internal instructions, the address lines do not change state. Figure 4-10 External Memory Interface Timing Figure 4-11 External Memory Interface Timing Operating Conditions ...
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Figure 4-11 External Memory Interface Timing (Continued) Operating Conditions SSIO SSA Characteristic RD Deasserted to Address Invalid Address Valid to RD Deasserted Valid Input Data Hold after RD Deasserted RD Assertion Width Address Valid ...
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Table 4-7 Reset, Stop, Wait, Mode Select, and Interrupt Timing Operating Conditions SSIO SSA Characteristic IRQA, IRQB Assertion to External Data Memory Access Out Valid, caused by first instruction execution in the interrupt service ...
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RESET t RAZ A0–A20, D0–D15 CS, RD, WR Figure 4-12 Asynchronous Reset Timing IRQA IRQB Figure 4-13 External Interrupt Timing (Negative-Edge-Sensitive IRW 56854 Technical Data, Rev RDA First Fetch First Fetch Freescale Semiconductor ...
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A0–A20, CS IDM IRQA, IRQB General Purpose I/O Pin t IG IRQA, IRQB Figure 4-14 External Level-Sensitive Interrupt Timing IRQA, IRQB A0–A20, CS, RD, WR Figure 4-15 Interrupt from Wait State Timing t IW IRQA A0–A20, ...
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RESET 4.8 Host Interface Port Table 4-8 Host Interface Port Timing Operating Conditions SSIO SSA Characteristic Access time Disable time Time to disassert Lead time Access time Disable time Disable time Setup time Hold ...
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HACK HD HREQ Figure 4-18 Controller-to-Host DMA Read Mode HA HCS HDS HRW HD Figure 4-19 Single Strobe Read Mode HA HCS HWR HRD HD Freescale Semiconductor TACKDV TREQACKL TACKREQH TRADV TRADV Figure 4-20 Dual Strobe Read Mode 56854 Technical ...
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HACK HD HREQ Figure 4-21 Host-to-Controller DMA Write Mode HA HCS HDS HRW HD Figure 4-22 Single Strobe Write Mode HA HCS HWR HRD HD 40 TDACKS TREQACKL TACKREQH TWDS TADSS TADSS TWDS TADSS TADSS Figure 4-23 Dual Strobe Write ...
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Serial Peripheral Interface (SPI) Timing Operating Conditions SSIO SSA Characteristic Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCLK) high time Master Slave Clock (SCLK) low ...
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SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) MOSI (Output) Figure 4-24 SPI Master Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) (ref) t ...
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SS (Input) SCLK (CPOL = 0) (Input) t SCLK (CPOL = 1) (Input) MISO (Output MOSI (Input) Figure 4-26 SPI Slave Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) t ...
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Quad Timer Timing Operating Conditions SSIO SSA Characteristic Timer input period Timer input high/low period Timer output period Timer output high/low period 1. In the formulas listed clock cycle. For f ...
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Table 4-11 ESSI Master Mode Operating Conditions SSIO SSA Parameter Delay from SCK high to SC2 (wl) high - Master Delay from SC0 high to SC1 (bl) high - Master Delay from SC0 high ...
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SCKH SCK output SC2 (bl) output t TFSWHM SC2 (wl) output t TXVM t STD SC0 output t RFSBHM SC1 (bl) output t RFSWHM SC1 (wl) output t SM SRD Figure 4-29 Master Mode Timing Diagram Table 4-12 ESSI ...
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Table 4-12 ESSI Slave Mode Operating Conditions SSIO SSA Parameter Delay from SCK high to SC2 (wl) high - Slave Delay from SC0 high to SC1 (bl) high - Slave Delay from SC0 high ...
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SCKH SCK input t TFSBHS SC2 (bl) input t TFSWHS SC2 (wl) input t FTXES t TXVS t TXES STD SC0 input t RFSBHS SC1 (bl) input t RFSWHS SC1 (wl) input t SS SRD Figure 4-30 Slave ...
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RXD SCI receive data pin (Input) TXD SCI receive data pin (Input) 4.13 JTAG Timing Operating Conditions SSIO SSA Characteristic 2 TCK frequency of operation TCK cycle time TCK clock pulse width TMS, TDI ...
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TCK (Input – Figure 4-33 Test Clock Input Timing Diagram TCK (Input) TDI TMS (Input) TDO (Output) TDO (Output ) Figure 4-34 Test Access Port Timing Diagram TRST (Input) DE ...
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GPIO Timing Operating Conditions SSIO SSA Characteristic GPIO input period GPIO input high/low period GPIO output period GPIO output high/low period 1. In the formulas listed clock cycle. For f 2. ...
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Part 5 Packaging 5.1 Package and Pin-Out Information 56854 This section contains package and pin-out information for the 128-pin LQFP configuration of the 56854. HDS PIN 103 HCS HREQ HACK D10 ...
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Table 5-1 56854 Pin Identification by Pin Number Pin Pin Signal Name No. No. 1 MISO 2 MOSI 3 SCK DDIO 6 V SSIO ...
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Table 5-1 56854 Pin Identification by Pin Number (Continued) Pin Pin Signal Name No. No HD0 31 HD1 32 HD2 54 Pin Signal Name No. 59 A14 91 60 A15 ...
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NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT ...
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Part 6 Design Considerations 6.1 Thermal Design Considerations An estimation of the chip junction temperature, T Equation Where ambient temperature ° package junction-to-ambient thermal resistance °C/W θJA ...
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As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection ...
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Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the V and GND circuits. DD ...
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... Part Voltage DSP56854 1.8V, 3.3V Low-Profile Quad Flat Pack (LQFP) DSP56854 1.8V, 3.3V Low-Profile Quad Flat Pack (LQFP) *This package is RoHS compliant. Freescale Semiconductor Pin Package Type Count 128 128 56854 Technical Data, Rev. 6 Electrical Design Considerations Frequency Order Number (MHz) 120 DSP56854FG120 120 DSP56854FGE * 59 ...
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... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc. 2005. All rights reserved. DSP56854 Rev. 6 01/2007 ...