adsp-21367kbpz-2a Analog Devices, Inc., adsp-21367kbpz-2a Datasheet - Page 2

• Manufacturer Part Number: adsp-21367kbpz-2a
• Description: Sharc Processors
• Manufacturer: Analog Devices, Inc.

ADSP-21367/ADSP-21368/ADSP-21369
KEY FEATURES—PROCESSOR CORE
At 333 MHz (3 ns) core instruction rate, the processors per-
2M bit on-chip, SRAM (0.75M bit in blocks 0 and 1, and
6M bit on-chip, mask-programmable ROM (3M bit in block 0
Dual data address generators (DAGs) with modulo and bit-
Zero-overhead looping with single-cycle loop setup, provid-
Single-instruction, multiple-data (SIMD) architecture
Transfers between memory and core at a sustained
INPUT/OUTPUT FEATURES
DMA controller supports:
form 2 GFLOPS/666 MMACS
0.25M bit in blocks 2 and 3) for simultaneous access by the
core processor and DMA
and 3M bit in block 1)
reverse addressing
ing efficient program sequencing
provides:
Two computational processing elements
Concurrent execution
Code compatibility with other SHARC family members at
Parallelism in buses and computational units allows: single
6.4G bytes/s bandwidth at 333 MHz core instruction rate
34 zero-overhead DMA channels for transfers between
32-bit DMA transfers at peripheral clock speed, in parallel
32-bit wide external port provides glueless connection to
Programmable wait state options: 2 SCLK to 31 SCLK cycles
Delay-line DMA engine maintains circular buffers in exter-
SDRAM accesses at 133 MHz and asynchronous accesses at
Shared-memory support allows multiple DSPs to automat-
Shared memory interface (ADSP-21368 only) support
Distributed on-chip bus arbitration for parallel bus
Four memory select lines allow multiple external memory
the assembly level
cycle executions (with or without SIMD) of a multiply
operation, an ALU operation, a dual memory read or
write, and an instruction fetch
internal memory and a variety of peripherals
with full-speed processor execution
both synchronous (SDRAM) and asynchronous memory
devices
nal memory with tap/offset-based reads
66 MHz
ically arbitrate for the bus and gluelessly access a
common memory device
provides:
Glueless connection for scalable DSP multiprocessing
architecture
Connect of up to four ADSP-21368 processors and global
memory
devices
Rev. A | Page 2 of 56 | August 2006
Digital audio interface (DAI) includes eight serial ports, four
Digital peripheral interface (DPI) includes three timers, two
Eight dual data line serial ports that operate at up to
TDM support for telecommunications interfaces including
Up to 16 TDM stream support, each with 128 channels per
Companding selection on a per channel basis in TDM mode
Input data port, configurable as eight channels of serial data
Signal routing unit provides configurable and flexible con-
2 muxed flag/IRQ lines
1 muxed flag/timer expired line /MS pin
1 muxed flag/IRQ /MS pin
DEDICATED AUDIO COMPONENTS
S/PDIF-compatible digital audio receiver/transmitter sup-
Four independent asynchronous sample rate converters
Pulse-width modulation provides:
ROM-based security features include:
PLL has a wide variety of software and hardware multi-
Dual voltage: 3.3 V I/O, 1.2 V or 1.3 V core
Available in 256-ball SBGA and 208-lead MQFP packages (see
precision clock generators, an input data port, an S/PDIF
transceiver, an 8-channel asynchronous sample rate con-
verter, and a signal routing unit
UARTs, two SPI ports, and a two wire interface port
Outputs of PCG's C and D can be driven on to DPI pins
50M bits/s on each data line—each has a clock, frame sync,
and two data lines that can be configured as either a
receiver or transmitter pair
128 TDM channel support for newer telephony interfaces
such as H.100/H.110
frame
or seven channels of serial data and up to a 20-bit wide
parallel data channel
nections between all DAI/DPI components
ports EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards
Left-justified, I
16-, 18-, 20- or 24-bit word widths (transmitter)
(SRC). Each converter has separate serial input and output
ports, a de-emphasis filter providing up to –140 dB SNR
performance, stereo sample rate converter (SRC) and sup-
ports left-justified, I
24, 20, 18, and 16 audio data word lengths
16 PWM outputs configured as four groups of four outputs
supports center-aligned or edge-aligned PWM waveforms
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
plier/divider ratios
Ordering Guide on Page
access under program control to sensitive code
2
S, or right-justified serial data input with
2
S, TDM, and right-justified modes and
56)