adsp-21367kbpz-2a Analog Devices, Inc., adsp-21367kbpz-2a Datasheet - Page 15

• Manufacturer Part Number: adsp-21367kbpz-2a
• Description: Sharc Processors
• Manufacturer: Analog Devices, Inc.

DATA MODES
The upper 32 data pins of the external memory interface are
muxed (using bits in the SYSCTL register) to support the exter-
nal memory interface data (input/output), the PDAP (input
only), the FLAGS (input/output), and the PWM channels (out-
put).
Table 6. Function of Data Pins
1
BOOT MODES
Table 7. Boot Mode Selection
CORE INSTRUCTION RATE TO CLKIN RATIO MODES
For details on processor timing, see
Figure 4 on Page
Table 8. Core Instruction Rate/CLKIN Ratio Selection
DATA PIN MODE
000
001
010
011
100
101
110
111
These signals can be FLAGS or PWM or a mix of both. However, they can be selected only in groups of four. Their function is determined by the control signals
BOOT_CFG1–0
00
01
10
CLK_CFG1–0
00
01
10
FLAGS/PWM_SEL. For more information, see the ADSP-21368 SHARC Processor Hardware Reference.
Table 6
provides the pin settings.
19.
Booting Mode
SPI Slave Boot
SPI Master Boot
EPROM/FLASH Boot
Core to CLKIN Ratio
6:1
32:1
16:1
Timing Specifications
FLAGS/PWM15–0
FLAGS/PWM15–0
FLAGS/PWM15–0
DATA31–16
Rev. A | Page 15 of 56 | August 2006
PDAP (DATA + CTRL)
PDAP (DATA + CTRL)
and
1
1
1
ADSP-21367/ADSP-21368/ADSP-21369
Three-state all pins
EPDATA32–0
Reserved
FLAGS15–8
DATA15–8
EPDATA15–0
FLAGS15–0
EPDATA7–0
EPDATA7–0
FLAGS7–0
DATA7–0