adsp-21364bbc Analog Devices, Inc., adsp-21364bbc Datasheet - Page 38

• Manufacturer Part Number: adsp-21364bbc
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
S/PDIF Transmitter
Serial data input to the S/PDIF transmitter can be formatted as
left-justified, I
20, or 24 bits. The following sections provide timing for the
transmitter. This feature is not available on the
ADSP-21363 models.
Figure 30
for the left channel and high for the right channel. Data is valid
on the rising edge of SCLK. The MSB is left-justified to an
LRCLK transition but with a single SCLK period delay.
Figure 31
left channel and low for the right channel. Data is valid on the
rising edge of SCLK. The MSB is left-justified to an LRCLK
transition with no MSB delay.
SDATA
SDATA
SDATA
LRCLK
LRCLK
LRCLK
SCLK
SCLK
SCLK
shows the default I
shows the left-justified mode. LRCLK is high for the
LSB
2
S, or right-justified with word widths of 16, 18,
MSB
MSB
MSB-1
MSB-1 MSB-2
MSB-2
2
S-justified mode. LRCLK is low
MSB
LSB+2
LEFT CHANNEL
LEFT CHANNEL
MSB-1
LSB+2 LSB+1
LSB+1
LEFT CHANNEL
MSB-2
LSB
LSB
Rev. D | Page 38 of 56 | April 2008
Figure 29. Right -Justified Mode
Figure 31. Left-Justified Mode
Figure 30. I
LSB+2 LSB+1
2
LSB
S-Justified Mode
MSB
RIGHT CHANNEL
MSB-1
MSB
S/PDIF Transmitter—Serial Input Waveforms
Figure 29
left channel and low for the right channel. Data is valid on the
rising edge of SCLK. The MSB is delayed 12-bit clock periods
(in 20-bit output mode) or 16-bit clock periods (in 16-bit output
mode) from an LRCLK transition, so that when there are
64 SCLK periods per LRCLK period, the LSB of the data will be
right-justified to the next LRCLK transition.
MSB-2
MSB-1
MSB-2
shows the right-justified mode. LRCLK is high for the
RIGHT CHANNEL
RIGHT CHANNEL
LSB+2
MSB
MSB-1 MSB-2
LSB+2
LSB+1
LSB+1
LSB
LSB
LSB+2
LSB+1
MSB
LSB
MSB+1
MSB