adsp-21364bbc Analog Devices, Inc., adsp-21364bbc Datasheet - Page 18

• Manufacturer Part Number: adsp-21364bbc
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Table 12. Clock Periods
1
Figure 6
lator or crystal. The shaded divider/multiplier blocks denote
where clock ratios can be set through hardware or software
using the power management control register (PMCTL). For
more information, see the ADSP-2136x SHARC Processor Hard-
ware Reference and Managing the Core PLL on Third-
Generation SHARC Processors (EE-290).
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
Timing
Requirements
t
t
t
t
t
where:
SR = serial port-to-peripheral clock ratio (wide range, determined by SPORT
CK
CCLK
PCLK
SCLK
SPICLK
CLKDIV)
SPIR = SPI-to-core clock ratio (wide range, determined by SPIBAUD register)
SCLK = serial port clock
SPICLK = SPI clock
shows core to CLKIN relationships with external oscil-
RESET
XTAL
BUF
CLKIN
4096 CLKIN
Description
CLKIN Clock Period
(Processor) Core Clock Period
(Peripheral) Clock Period = 2 × t
Serial Port Clock Period = (t
SPI Clock Period = (t
DELAY OF
CYCLES
DIVIDER
PMCTL
CLKIN
1
PLLI
CLK
RESETOUT
Figure 6. Core Clock and System Clock Relationship to CLKIN
CCLK
) × SPIR
CCLK
Rev. D | Page 18 of 56 | April 2008
CLKOUT
) × SR
CCLK
CLK_CFGx/PMCTL
FILTER
LOOP
MULTIPLIER
PLL
PLL
VCO
not meaningful to add parameters to derive longer times. See
Figure 39 on Page 45
reference levels.
Note that in the user application, the PLL multiplier value
should be selected in such a way that the VCO frequency never
exceeds f
lated as follows:
where:
f
PLLM is the multiplier value programmed.
f
f
f
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
VCO
INPUT
INPUT
INPUT
DIVIDER
f
is the VCO frequency.
VCO
PLL
is the input frequency to the PLL.
= CLKIN when the input divider is disabled and
= CLKIN ÷ 2 when the input divider is enabled.
VCO
= 2 × PLLM × f
specified in
CLK_CFGx/
PMCTL
PMCTL
under Test Conditions for voltage
INPUT
Table
DIVIDE
BY 2
BUF
14. The VCO frequency is calcu-
RESETOUT
CCLK
PCLK
CLKOUT
CORERST