dac3555a Micronas, dac3555a Datasheet - Page 10

• Manufacturer Part Number: dac3555a
• Description: Stereo Audio Dac
• Manufacturer: Micronas

DAC 3555A
2.11. I
The DAC 3555A is equipped with an I
interface. The I
addressing: The I
the IC. The subaddress allows chip select in multi DAC
applications and selects one of the three internal regis-
ters. The registers are write-only. The I
address is given below.
Device Address = 4D
The registers of the DAC 3555A have 8- or 16-bit data
size; 16-bit registers are accessed by writing two 8-bit
data words.
2.12. Registers
In Section 3.5. “Control Registers” on page 18, a defi-
nition of the DAC 3555A control registers is shown. A
hardware reset initializes all control registers to 0. The
automatic chip initialization loads a selected set of reg-
isters with the default values given in the table.
All registers are write-only.
The register address is coded by 3 bits (RA1, RA0)
according to Table 2–3.
Fig. 2–1: I
10
S
S
SDA
SCL
4D
2
4D
C Bus Interface
hex
hex
2
C bus protocols for write operations
2
S
C bus interface uses one level of sub-
w
w
2
C bus address is used to address
Ack sub_adr
Ack sub_adr
hex
.
Ack
Ack 1 byte data
1
0
2
C bus slave
2
C bus chip
1 byte data
Table 2–3: I
2.13. Chip Select
Chip select allows to connect up to four DAC 3555A to
an I
by the MCS1/MCS2 (Mode and Chip Select) pins.
Only in standard mode, chip select is possible. MPEG
mode always uses chip subaddress 3.
Register address and chip select are mapped into the
subaddress field in Table 2–4.
Table 2–4: I
Ack P
Ack
RA1
0
1
1
7
MCS2
P
2
C control bus. The chip subaddresses are defined
1 byte data
6
MCS1
2
2
8-bit I
C Register Address
C Subaddress
2
RA0
1
0
1
W
R
Ack
Nak
S
P
C write access
5
Ack
=
=
=
=
=
=
PRELIMINARY DATA SHEET
4
0
1
0
1
Start
Stop
P
3
16-bit I
2
Mnemonics
SR_REG
AVOL
GCFG
2
C write access
1
RA1
Micronas
0
RA0