dac3555a Micronas, dac3555a Datasheet

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dac3555a

Manufacturer Part Number
dac3555a
Description
Stereo Audio Dac
Manufacturer
Micronas
Datasheet
Edition Jan. 8, 2002
6251-575-1PD
MICRONAS
DAC 3555A
Stereo Audio DAC
PRELIMINARY DATA SHEET
MICRONAS

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dac3555a Summary of contents

Page 1

... MICRONAS Edition Jan. 8, 2002 6251-575-1PD PRELIMINARY DATA SHEET DAC 3555A Stereo Audio DAC MICRONAS ...

Page 2

... Recommended Operating Conditions 23 3.6.3. Characteristics 28 4. Applications 28 4.1. Line Output Details 28 4.2. Recommended Low-Pass Filters for Analog Outputs 29 4.3. Recommendations for Filters and Deemphasis 29 4.4. Recommendations for MegaBass Filter without Deemphasis 30 4.5. Power-up/down Sequence 30 4.5.1. Power-up Sequence 30 4.5.2. Power-down Sequence 31 4.6. Typical Applications 34 5. Data Sheet History 2 PRELIMINARY DATA SHEET Micronas ...

Page 3

... I S Filter DRI SDA SCL Fig. 1–1: Block diagram of the DAC 3555A Micronas – SNR of 103 dB( – bus bus – internal clock oscillator – sample rates from 8 kHz to 96 kHz – analog deemphasis for 44.1 kHz – analog volume and balance: +18… and mute ...

Page 4

... MP3, WMA, AAC UART SD-Card, MMC Compact Flash Microdrive IDE R/W Fig. 1–2: Typical application: Secure Music Player clock input DAC 3555A SDMI compliant 1) only necessary for automatic sample rate detection PRELIMINARY DATA SHEET Line Out Line in Line in Micronas ...

Page 5

... XTO 13 Osc. XTI 12 AUX2L 29 AUX1L 31 DEEML 34 FOPL 38 FOUTL 37 FINL 39 Fig. 1–3: Block diagram of the DAC 3555A Micronas CLI DAI WSI Interpolation Filter Variable S & H 3rd-order Noise Shaper & Multibit DAC Analog Low-pass Filter Input Select Switch Matrix Postfilter Op Amps ...

Page 6

... PRELIMINARY DATA SHEET 2 S interface to make use of the full 2 S format defines an audio frame always C control allows changing the polarity of WSI format requires a delay of one clock 2 C control right 32-bit audio sample Micronas ...

Page 7

... The analog low-pass is a first order filter with a cut-off frequency of approximately 1.4 MHz which removes the high-frequency components of the noise-shaping signal. Micronas 2.6. Input Select and Mixing Matrix This block is used to switch between or mix the auxil kHz is iary inputs and the signals coming from the DAC. A ...

Page 8

... Table 2–1: Volume Control Volume/dB 18.0 16.5 15.0 13.5 0.0 1.5 serial resistors in 54.0 57.0 75 Mute PRELIMINARY DATA SHEET OUTL + Speaker 1.5 k > > … … Headphones AVDD 1 (HP-switch) OUTR AVOL 111000 110111 110110 110101 101100 (default) 101011 001000 000111 000001 000000 Micronas AVDD AVDD 32 … ...

Page 9

... Stan- ADR2 dard 1 1 MPEG ADR3 Micronas 2.10.1. Standard Mode In standard mode, sample rates from 48 kHz to 32 kHz are handled without I ting for this range is the default setting. Other sample rates require an I ensures that even at low sample rates, the DAC 3555A runs at a high clock rate. This avoids audi- ...

Page 10

... Ack 1 byte data Ack 1 byte data PRELIMINARY DATA SHEET 2 C Register Address RA0 Mnemonics 1 SR_REG 0 AVOL 1 GCFG 2 C Subaddress RA1 2 8-bit I C write access Ack P 2 16-bit I C write access = Ack = Nak = Start Stop Micronas 0 RA0 ...

Page 11

... Only the analog back-end is active. 4. Full Power All blocks are active in this mode. Start-up sequence: The recommended sequence for stepping through the power modes is shown in Section 4.5. “Power-up/down Sequence” on page 30. Micronas DAC 3555A 2.15. Oscillator 2 The I C-controlled oscillator (see Section 3.5. “Control Registers” ...

Page 12

... Fig. 3–1: 44-Pin Plastic Metric Quad Flat Package (PMQFP44) Weight approximately 0.4 g Dimensions in mm Fig. 3–2: 40-Pin Plastic Quad Flat No leads package (PQFN40) Weight approximately 0.096 g Dimensions 0 0.1 0.17 0.06 0.8 2.0 0.1 10 0.1 0.1 2.15 0.2 SPGS706000-5(P44)/1E PRELIMINARY DATA SHEET exposed die pad SPGS709000-1(P40)/2E Micronas ...

Page 13

... MCS1 20 9 MCS2 21 10 DEECTRL CLI 24 12 DAI 25 13 WSI Micronas Type Connection Short Description (If not used) IN/OUT X Analog reference Voltage IN X VSS 1 for audio back-end IN X VSS 0 for audio output amplifiers LV Not connected OUT LV Audio Output: Headphone left or ...

Page 14

... Filter op amp inverting input, left IN/OUT X Input for FOUTL or filter op amp output (line out) LV Not connected OUT X Output to right external filter IN/OUT X Right Filter op amp inverting input IN/OUT X Input for FOUTR or filter op amp output (line out Analog reference Ground PRELIMINARY DATA SHEET Micronas ...

Page 15

... The AUX pins provide two analog stereo inputs. Auxil- iary input signals, e.g. the output of a conventional receiver circuit or the output of a tape recorder can be connected with these inputs. The input signals have to be connected by capacitive coupling. Micronas DAC 3555A FOUTL FOPL FINL ...

Page 16

... OUTL DAC 3555A XTI DEECTRL XTO MCS2 CLKOUT MCS1 SCL VDD SDA VSS the AUX1R AUX1L AUX2R AUX2L NC TESTEN PORQ WSI DAI CLI Micronas ...

Page 17

... AGNDC Fig. 3–7: Pins FINR, FOPR, FINL, FOPL, DEEML, DEEMR OUTn AGNDC Fig. 3–8: Output Pins OUTL, OUTR Micronas AGNDC Fig. 3–9: Output Pins FOUTL, FOUTR AVSS0/1 Fig. 3–10: Pins AGNDC, VREF Fig. 3–11: Input/Output Pins XTI, XTO AUXnL AGNDC ...

Page 18

... PRELIMINARY DATA SHEET Default Name Values (hex) 0 hex LR_SEL 1) 1) SP_SEL SRC_48 SRC_32 SRC_24 SRC_16 SRC_12 SRC_8 SRC_96 3) SRC_A 0 hex OSC DEEM AVOL_L AVOL_R Micronas ...

Page 19

... PRELIMINARY DATA SHEET Sub- Number Mode address of Bits (hex) Global Configuration GCFG don’t care Micronas Function global configuration bit[7] select mode bit[6:4] DAC and Power-Mode bit[6] bit[5] bit[ DAC off - Zero Power ...

Page 20

... Pin Name 1) AVDD0/1 VDD MCS1, MCS2, DEECTRL WSI, CLI, DAI, PORQ, SCL, SCI 2) OUTL/R 3) PRELIMINARY DATA SHEET Min. Max. Unit 125 C 500 0.3 V SUPD 0 0 0.3 V SUPA 0.2 0 Micronas ...

Page 21

... All data sheet parameters are valid for normal operating temperature range, only. 2) typically operable down to 2.7 V, without loss of performance Please refer to Section 4.2. “Recommended Low-Pass Filters for Analog Outputs” on page 28. Micronas Pin Name Min AVDD0/1 3 ...

Page 22

... OUTL/R OUTL/R SCL CLI, 0.5 WSI, VDD DAI, PORQ, SCL, SDA XTI XTI CLI 45 CLI 40 13.3 CLKOUT 0 PRELIMINARY DATA SHEET Typ. Max. Unit k 1 400 100 pF 400 kHz V 0.2 V VDD 0.25 V VDD max 0.75 V VDD min 14.725 17 MHz Micronas ...

Page 23

... Current Consumption AVDD Analog Audio active, 32-bit mode kHz traffic 3) 2 DAC on active, 32-bit mode kHz, 1 kHz @ 0 dB Micronas = 3.0 to 5.5 V; typical values at T SUPA Pin Name Min. Typ. Max. VDD 3.7 5.0 7.0 5.0 DAI, TESTEN, PORQ, DEECTRL, ...

Page 24

... AUXnL/R rms mW SEL_53V = Analog Gain = +3 dB, distortion < 1%, external 47 series resistor required mW SEL_53V = (bridged) L Analog Gain = +3 dB, distortion < 10%, SEL_53V = 0, IRPA = 1 mW SEL_53V = Analog Gain: 75 dB... Analog Gain: 54 dB...+ 46.5 dB Analog Gain 54 dB Micronas ...

Page 25

... Signal-to-Noise Ratio 1 SNR Signal-to-Noise Ratio 2 Lev Mute Level Mute R D/A Pass Band Ripple D/A A D/A Stop Band Attenuation D/A BW Bandwidth for AUX Auxiliary Inputs Hz...22 kHz kHz Micronas Pin Name Min. Typ. Max. OUTL OUTL/R 0.5 0.5 OUTL/R 0.5 0.5 AUXn, 98 FINL/R AUXn, 93 OUTn ...

Page 26

... Analog Gain = 0 dB, Input = 0 AUXnL/R rms kHz, sine wave, FOUTL/R: R > 7 OUTL/ (47 series resistor required) Analog Gain = 0 dB, Input = 3 dB and FS 0 AUXnL/R rms V SEL_53V = referred to VREF V SEL_53V = referred to VREF Micronas ...

Page 27

... Offset Voltage at Input Pins OffI V Offset Voltage at OffO Output Pins V Offset Voltage at OffFO Filter Output Pins V Offset Voltage at OffFI Filter Input Pins dV Difference of DC Voltage at DCPD Output Pins Hz...22 kHz kHz Micronas Pin Name Min. Typ. Max. AUXnL/R 12.1 15 17.9 11.6 19.0 24.2 30 35.8 23.3 37.9 OUTL/R 700 FINL 15 FINR 11 ...

Page 28

... FOUTL(R) FINL(R) Fig. 4–3: 3rd-order low-pass filter Table 4–4: Attenuation of 3rd-order low-pass filter Frequency 18 kHz 24 kHz 30 kHz PRELIMINARY DATA SHEET 220 pF 1.0 nF AVSS FOPL(R) FINL(R) - Gain 1 120 pF 7.5 k 7.5 k 1.8 nF AVSS FOPL(R) FINL(R) - Gain 0.17 dB 0.23 dB 3.00 dB Micronas ...

Page 29

... (pF) 180 180 (nF) 1.8 1.0 Micronas 4.4. Recommendations for MegaBass Filter without Deemphasis R5 C4 FOUTL(R) FINL(R) DEEML(R) Fig. 4–1: General circuit schematic Table 4–6: Resistor and Capacitor values 3rd order 7.5 560 7.5 C1 (nF) 270 ...

Page 30

... Aux to Line muted DAC off Aux to Line unmuted 2 S input, it should be done here PRELIMINARY DATA SHEET VDD PORQ 0.6 VDD DD AVDD0/1 DD Wait Period 0 DAC on Full Power muted DAC on Full Power unmuted Micronas ...

Page 31

... PRELIMINARY DATA SHEET 4.6. Typical Applications Fig. 4–4: Application circuit schematic 1: Standard application with analog deemphasis. Oscillator not needed. Package: PMQFP44 Micronas DAC 3555A 31 ...

Page 32

... DAC 3555A Fig. 4–5: Application circuit schematic 2: MPEG application with analog Megabass and 14.31818 MHz clock input. Package: PMQFP44 32 PRELIMINARY DATA SHEET Micronas ...

Page 33

... PRELIMINARY DATA SHEET Micronas DAC 3555A 33 ...

Page 34

... By this publication, Micronas GmbH does not assume responsibil- ity for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. ...

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