x9271uvi-2.7 Intersil Corporation, x9271uvi-2.7 Datasheet

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x9271uvi-2.7

Manufacturer Part Number
x9271uvi-2.7
Description
Single Digitally-controlled Xdcp? Potentiometer
Manufacturer
Intersil Corporation
Datasheet
Single Digitally-Controlled (XDCP™)
Potentiometer
FEATURES
• 256 Resistor Taps
• SPI Serial Interface for write, read, and transfer
• Wiper Resistance, 100Ω typical @ V
• 16 Nonvolatile Data Registers
• Nonvolatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position on
• Standby Current < 3µA Max
• V
• 50kΩ, 100kΩ versions of End to End Resistance
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes per Bit per
• 14-Lead TSSOP
• Low Power CMOS
• Pb-Free Plus Anneal Available (RoHS Compliant)
FUNCTIONAL DIAGRAM
operations of the potentiometer
Power-up.
Register
CC
: 2.7V to 5.5V Operation
Interface
SPI
Bus
Address
Status
Data
®
1
Data Sheet
and Control
Interface
Bus
V
V
SS
CC
CC
= 5V
Transfer
Inc/Dec
Control
Write
Read
1-888-INTERSIL or 1-888-352-6832
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
Power-on Recall
Data Registers
Wiper Counter
Register (WCR)
Single Supply/Low Power/256-Tap/SPI Bus
16 Bytes
DESCRIPTION
The X9271 integrates a single digitally controlled
potentiometer
integrated circuit.
The digital controlled potentiometer is implemented
using 255 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. The potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and a four
nonvolatile Data Registers that can be directly written to
and read by the user. The contents of the WCR controls
the position of the wiper on the resistor array though the
switches. Powerup recalls the contents of the default
data register (DR0) to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
November 22, 2005
All other trademarks mentioned are the property of their respective owners.
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
R
(XDCP)
W
R
R
H
L
50kΩ and 100kΩ
POT
on
256-taps
a
monolithic
X9271
FN8174.2
CMOS

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x9271uvi-2.7 Summary of contents

Page 1

Data Sheet Single Digitally-Controlled (XDCP™) Potentiometer FEATURES • 256 Resistor Taps • SPI Serial Interface for write, read, and transfer operations of the potentiometer • Wiper Resistance, 100Ω typical @ V • 16 Nonvolatile Data Registers • Nonvolatile Storage ...

Page 2

Ordering Information PART NUMBER PART MARKING X9271UV14* X9271UV X9271UV14I* X9271UV I X9271UV14IZ* (Note) X9271UV ZI X9271UV14Z* (Note) X9271UV Z X9271TV14* X9271TV X9271TV14I* X9271TV I X9271TV14IZ* (Note) X9271TV ZI X9271TV14Z* (Note) X9271TV Z X9271UV14-2.7* X9271UV F X9271UV14I-2.7* X9271UV G X9271UV14IZ-2.7* (Note) ...

Page 3

DETAILED FUNCTIONAL DIAGRAM V CC HOLD CS SCK INTERFACE SO AND CONTROL SI CIRCUITRY CIRCUIT LEVEL APPLICATIONS • Vary the gain of a voltage amplifier • Provide programmable dc reference voltages for comparators and detectors ...

Page 4

PIN CONFIGURATION TSSOP X9271 SCK PIN ASSIGNMENTS TSSOP Symbol SCK ...

Page 5

PIN DESCRIPTIONS Bus Interface Pins S O (SO) ERIAL UTPUT serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. ...

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PRINCIPLES OF OPERATION Device Description S I ERIAL NTERFACE The X9271 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS must be LOW and the HOLD ...

Page 7

DEVICE DESCRIPTION Wiper Counter Register (WCR) The X9271 contains a Wiper Counter Register for the DCP potentiometer. The Wiper Counter Register can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of ...

Page 8

DEVICE DESCRIPTION Instructions I B (ID A) DENTIFICATION YTE AND The first byte sent to the X9271 from the host, following a CS going HIGH to LOW, is called the Identification byte. The most significant four bits of the slave ...

Page 9

Table 5. Instruction Byte Format Instruction Opcode (MSB) DEVICE DESCRIPTION Instructions Five of the eight instructions are three bytes in length. These instructions are: – Read Wiper Counter Register – read the current wiper position of the ...

Page 10

Figure 2. Two-Byte Instruction Sequence CS SCK ID3 ID2 ID1 ID0 Device ID Figure 3. Three-Byte Instruction Sequence (Write) CS SCL ID3 ID2 ID1 ID0 ...

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Figure 5. Increment/Decrement Instruction Sequence CS SCL ID3 ID2 ID1 ID0 0 0 Internal Device ID Address Figure 6. Increment/Decrement Timing Limits SCK INC/DEC CMD ISSUED Table 6. Instruction Set ...

Page 12

INSTRUCTION FORMAT Read Wiper Counter Register (WCR) Device Type Device Identifier Addresses CS Falling Edge Write Wiper Counter Register (WCR) Device Type Device Identifier Addresses CS ...

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Transfer Data Register (DR) to Wiper Counter Register (WCR) Device Type Device CS Identifier Addresses Falling Edge Increment/Decrement Wiper Counter Register (WCR) Device Type Device CS Identifier Addresses Falling Edge ...

Page 14

ABSOLUTE MAXIMUM RATINGS Temperature under bias..................... -65°C to +135°C Storage temperature ......................... -65°C to +150°C Voltage on SCK any address input with respect to V ................................. -1V to +7V SS ∆ )|..................................................... 5. Lead ...

Page 15

D.C. OPERATING CHARACTERISTICS Symbol Parameter I V supply current CC1 CC (active supply current CC2 CC (nonvolatile write current (standby Input leakage current LI I Output leakage current LO V Input HIGH voltage ...

Page 16

EQUIVALENT A.C. LOAD CIRCUIT 5V 1462Ω SO pin 2714Ω 100pF AC TIMING Symbol f SSI/SPI clock frequency SCK t SSI/SPI clock cycle time CYC t SSI/SPI clock high time WH t SSI/SPI clock low time WL t Lead time LEAD ...

Page 17

HIGH-VOLTAGE WRITE CYCLE TIMING Symbol t High-voltage write cycle time (store instructions) WR XDCP TIMING Symbol t Wiper response time after the third (last) power supply is stable WRPO t Wiper response time after instruction issued (all load instructions) WRL ...

Page 18

TIMING DIAGRAMS Input Timing CS t LEAD SCK MSB SI High Impedance SO Output Timing CS SCK t V MSB SO ADDR SI Hold Timing CS SCK HOLD 18 X9271 t CYC ...

Page 19

XDCP Timing (for All Load Instructions) CS SCK MSB SI VWx High Impedance SO Write Protect and Device Address Pins Timing X9271 ... t WRL ... (Any Instruction WPASU WPAH LSB FN8174.2 November ...

Page 20

APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers V R Three terminal Potentiometer; Variable voltage divider Application Circuits Noninverting Amplifier – (1 Offset Voltage Adjustment R 1 ...

Page 21

Application Circuits (continued) Attenuator – -1/2 ≤ G ≤ +1/2 Inverting Amplifier ...

Page 22

... Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...

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