X9271-2.7 INTERSIL [Intersil Corporation], X9271-2.7 Datasheet
X9271-2.7
Related parts for X9271-2.7
X9271-2.7 Summary of contents
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... Bus Interface and Control 1 Single Supply/Low Power/256-Tap/SPI Bus March 31, 2005 DESCRIPTION The X9271 integrates a single digitally controlled potentiometer integrated circuit. The digital controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to the wiper = 5V CC terminal through switches ...
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... Set the scale factor and zero point in sensor signal conditioning circuits • Vary the frequency and duty cycle of timer ICs • Vary the dc biasing of a pin diode attenuator in RF circuits • Provide a control variable ( feedback circuits 2 X9271 Power-on Recall Bank WIPER ...
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... HOLD X9271 HOLD A1 WP Serial Data Output. Device Address. No Connect. Chip Select. Serial Clock. Serial Data Input. System Ground. Hardware Write Protect. Device Address. Device select. Pause the serial bus. ...
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... S (CS) HIP ELECT When CS is HIGH, the X9271 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables the X9271, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition required prior to the start of any operation ...
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... This can help to reduce system pin count RRAY ESCRIPTION The X9271 is comprised of a resistor array (See Figure 1). The array contains the equivalent of 255 discrete resistive segments that are connected in Figure 1. Detailed Potentiometer Block Diagram SERIAL DATA PATH FROM INTERFACE ...
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... Finally loaded with the contents of its Data Register zero (DR0) upon power-up. The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9271 is powered- down. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down ...
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... CS going HIGH to LOW, is called the Identification byte. The most significant four bits of the slave address are a device type identifier. The ID[3:0] bits is the device id for the X9271; this is fixed as 0101[B] (refer to Table 4). The bits in the ID byte is the internal slave address ...
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... RB RA Two instructions require a two-byte sequence to complete (Figure 2). These instructions transfer data between the host and the X9271; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: – XFR Data Register to Wiper Counter Register – ...
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... A1 A0 Internal Device ID Address Figure 4. Three-Byte Instruction Sequence (Read) CS SCL ID3 ID2 ID1 ID0 Internal Device ID Address S0 9 X9271 Internal Instruction Address Opcode Instruction Register Pot/Bank Address Opcode ...
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... Write Data Register 1 XFR Data Register to 1 Wiper Counter Register XFR Wiper Counter 1 Register to Data Register Increment/Decrement 0 Wiper Counter Register Read Status (WIP bit) 0 Note: 1/0 = data is one or zero 10 X9271 Instruction Register Opcode Address VOLTAGE OUT Instruction Set I2 I1 ...
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... Data Byte Rising Edge Data Byte CS (Sent by X9271 on SO) Rising Edge Data Byte (Sent by Host on SI) CS Rising Edge CS HIGH-VOLTAGE WRITE CYCLE FN8174.1 March 31, 2005 ...
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... Instruction DR/Bank Opcode Addresses I/D I/D Instruction DR/Bank Opcode Addresses Rising Edge Increment/Decrement CS (Sent by Master on SDA) Rising Edge . . . . I/D I/D Data Byte CS (Sent by X9271 on SO) Rising Edge WIP FN8174.1 March 31, 2005 ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Max. Device +70°C X9271 +85°C X9271-2.7 Limits Min. Typ. Max. 100 50 ±20 50 ±3 ...
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... Notes: (6) This parameter is not 100% tested (7) t and t are the delays required from the time the (last) power supply (V PUR PUW These parameters are periodically sampled and not 100% tested. 14 X9271 (Over the recommended operating conditions unless otherwise specified.) Limits Min. Typ. Max. 400 1 ...
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... HZ t HOLD high to output in low Noise suppression time constant at SI, SCK, HOLD and CS inputs deselect time CS t WP, A0 setup time WPASU t WP, A0 hold time WPAH 15 X9271 3V 1382Ω SO pin 1217Ω 100pF Parameter SPICE Macromodel R TOTAL ...
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... WAVEFORM INPUTS Must be steady May change from Low to High May change from High to Low Don’t Care: Changes Allowed N/A 16 X9271 Parameter Parameter OUTPUTS Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line ...
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... TIMING DIAGRAMS Input Timing CS t LEAD SCK MSB SI High Impedance SO Output Timing CS SCK t V MSB SO ADDR SI Hold Timing CS SCK HOLD 17 X9271 t CYC ... ... ... t HO ... t t HSU HH ... HOLD LAG t RI LSB t DIS ...
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... XDCP Timing (for All Load Instructions) CS SCK MSB SI VWx High Impedance SO Write Protect and Device Address Pins Timing X9271 ... t WRL ... (Any Instruction WPASU WPAH LSB FN8174.1 March 31, 2005 ...
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... Offset Voltage Adjustment 100kΩ – + TL072 10kΩ 10kΩ 10kΩ +12V -12V 19 X9271 Comparator with Hysterisis Two terminal Variable Resistor; Variable current Voltage Regulator ...
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... G ≤ +1/2 Inverting Amplifier – Function Generator – + frequency ∝ amplitude ∝ X9271 10kΩ Filter – ...
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... PACKAGING INFORMATION See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 21 X9271 14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V .025 (.65) BSC .169 (4.3) .177 (4.5) .193 (4.9) .200 (5.1) .0075 (.19) .002 (.05) .0118 (.30) .006 (.15) 0° ° .019 (.50) .029 (.75) Detail A (20X) .252 (6.4) BSC .047 (1.20) .010 (.25) Gage Plane Seating Plane ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 22 X9271 ...