tda8757c NXP Semiconductors, tda8757c Datasheet - Page 22

• Manufacturer Part Number: tda8757c
• Description: Tda8757c Triple 8-bit Adc 205 Msps
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 10111
Preliminary data
9.1.8 DEMUX register
9.1.9 Power-down mode
9.2 I
Table 11:
The default programmed value is as follows:
The default programming is:
For timing diagrams concerning various settings of this register, see
Table 12:
The address of the circuit for the I
Bits ‘A1’ and ‘A0’ are fixed by the potential on pins A2 and A1. Bit ‘RW’ must always
be equal to logic 0 because it is not possible to read the data in the register. The
timing and protocol for the I
see
P4
0
0
...
1
1
2
•
•
•
•
•
•
•
•
•
•
•
•
A6
1
C-bus protocol
No external clock: bit ‘Ckext’ is logic 0
Phase shift for CKDATA is 0 deg.
Outputs forced to logic 0 during CLP and HSYNC pulses: bit ‘Blk’ = 1
First pixel not shifted: bit ‘Shpixel’ = 0
CKREFO with positive polarity: bit ‘Ckrp’ = 0
CKDATA not reversed: bit ‘Ckdp’ = 0
CKDATA not delayed: bit ‘Ckdd’ = 0
Interleaved outputs: bit ‘Shift’ = 1
Odd pixels on port A: bit ‘Odda’ = 1.
Demultiplexed outputs: bit ‘Dmx’ = 1
When the supply is disconnected, the registers are reset to their default values;
they require reprogramming if the settings are different (e.g. through an EEPROM)
When the device is in Power-down mode (bit PWD = 1), all data and clock outputs
are in high-impedance.
Table 13
Phase registers bits
Register format
A5
0
and 14.
P3
0
0
...
1
1
Rev. 01 — 14 August 2002
A4
0
P2
0
0
...
1
1
2
C-bus are standard. Two sequences are available;
A3
1
2
C-bus is 1001 1XX0.
P1
0
0
...
1
1
A2
1
P0
0
1
...
0
1
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
A1
A2
Triple 8-bit ADC 205 Msps
TDA8757C
A0
A1
0
...
Phase shift (deg)
11.25
337.5
348.75
Figure 11
RW
0
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