cs5421 ON Semiconductor, cs5421 Datasheet - Page 13

• Manufacturer Part Number: cs5421
• Description: Dual Outofphase Synchronous Buck Controller With Remote Sense
• Manufacturer: ON Semiconductor

manufacturer’s data sheets. Its value is dependent on the
mold compound and lead frames used in assembly of the
semiconductor device in question.
to the heatsink. This component of the thermal resistance is
dependent on the roughness of the heatsink and component
as well as on the pressure applied between the two. Θ
be reduced by using thermal pads or by applying a thin layer
of thermal grease between the case and the heatsink. Such
materials reduce the air gap normally found between the
heatsink and the case and provide a better path for thermal
energy. Values of Θ
manufacturers of heatsinks and thermal compounds.
to the ambient environment. Θ
when selecting a heatsink. Low values of Θ
increased power dissipation without exceeding the
maximum junction temperature of the component. Values of
Θ
manufacturers.
where:
required to keep the calculated junction temperature at the
given level of power dissipation below the component
manufacturer’s maximum junction temperature.
at high frequency, switching regulators generate noise as a
consequence of their normal operation. When designing for
compliance with EMI/EMC regulations, additional
components may be added to reduce noise emissions. These
components are not required for regulator operation and
experimental results may allow them to be eliminated. The
SA
Θ
The value for Θ
Θ
Finally, Θ
The basic equation for selecting a heatsink is:
P
T
T
Θ
Θ
Θ
The choice of heatsink is dependent on the value of Θ
As a consequence of large currents being turned on and off
D
A
J
SA
CS
JC
CS
SA
= IC or FET junction temperature (in degrees C);
= power dissipated by part in question (in watts);
= ambient temperature (in degrees C);
are found in catalogs published by heatsink
= the junction−to−case thermal resistance (in degrees
= the sink−to−ambient thermal resistance (in degrees
is the thermal impedance from the surface of the case
= the case−to−sink thermal resistance (in degrees C
= the sink−to−ambient thermal resistance (in degrees
C per watt);
C per watt).
C per watt).
per watt);
SA
is the thermal impedance from the heatsink
P +
EMI MANAGEMENT
CS
Q JC ) Q CS ) Q SA
JC
are found in catalogs published by
is included in the component
T J * T A
SA
is the important parameter
SA
http://onsemi.com
CS
allow
can
SA
13
input filter inductor may not be required because bulk filter
and bypass capacitors, as well as other loads located on the
board will tend to reduce regulator di/dt effects on the circuit
board and input power supply. Placement of the power
component to minimize routing distance will also help to
reduce emissions.
circuit board, the following checklist should be used to
ensure proper operation of the CS5421.
10. Place the output capacitors as close to the load as
11. Place the COMP capacitor as close as possible to the
12. Connect the filter components of the following pins:
13. Place the V
When laying out the CPU buck regulator on a printed
1. Rapid changes in voltage across parasitic capacitors
2. Keep high currents out of sensitive ground
3. Avoid ground loops as they pick up noise. Use star or
4. For high power buck regulators on double−sided
5. Even though double sided PCB’s are usually
6. Keep the inductor switching node small by placing
7. The MOSFET gate traces to the IC must be short,
8. Use fewer, but larger output capacitors, keep the
9. Place the switching MOSFET as close to the +5.0 V
and abrupt changes in current in parasitic inductors
are major concerns for a good layout.
connections.
single point grounding.
PCB’s a single ground plane (usually the bottom) is
recommended.
sufficient for a good layout, four−layer PCB’s are the
optimum approach to reducing susceptibility to
noise. Use the two internal layers as the power and
GND planes, the top layer for power connections and
component vias, and the bottom layers for the noise
sensitive traces.
the output inductor, switching and synchronous FETs
close together.
straight, and wide as possible.
capacitors clustered, and use multiple layer traces
with heavy copper to keep the parasitic resistance
low.
input capacitors as possible.
possible.
COMP pin.
V
trace, and connect this local GND trace to the output
capacitor GND.
to the IC.
FB
, V
OUT
LAYOUT GUIDELINES
, and COMP to the GND pin with a single
CC
bypass capacitors as close as possible