cs5421 ON Semiconductor, cs5421 Datasheet
cs5421
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cs5421 Summary of contents
Page 1
... V ™ control method to achieve the fastest possible transient response and best overall regulation, while using the least number of external components. The CS5421 features out−of−phase synchronization between the channels, reducing the input filter requirement. The CS5421 also provides undervoltage lockout, Soft Start, built in adaptive FET non− ...
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... Voltage Feedback Input for FB1 FB2 Channel Fast Voltage Feedback FB1 FB2 Input for Channel 1.0 μ GATE(H)2 GATE(H)1 2 GATE(L)2 GATE(L)2 CS5421 3 PGND2 PGND1 FFB1 FFB2 8 COMP1 COMP2 V FB2 FB1 OSC LGND SGND 4 5 ...
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ABSOLUTE MAXIMUM RATINGS (continued) Pin Symbol R Oscillator Resistor OSC GATE(H)1 GATE(H)2 High−Side FET Driver , for Channel GATE(L)1 GATE(L)2 Low−Side FET Driver for , Channel PGND1 Power Ground for Channel 1 PGND2 Power ...
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ELECTRICAL CHARACTERISTICS (continued) 10.8 V < V < 13 GATE(H)1,2 GATE(L)1,2 Characteristic PWM Comparator Transient Response PWM Comparator Offset Artificial Ramp V Bias Current FFB1(2) V Input Range FFB1(2) Minimum Pulse Width Oscillator Switching Frequency ...
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PACKAGE PIN DESCRIPTION (continued) PACKAGE PIN # 16 Lead SO Narrow BIAS V FFB1 V FFB2 + 8 − − Set Dominant − ...
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... THEORY OF OPERATION The CS5421 is a dual power supply controller that utilizes 2 the V control method. Two synchronous V can be built using a single controller. The fixed−frequency architecture, driven from a common oscillator, ensures a 180° phase differential between channels Control Method 2 The V method of control uses a ramp signal that is generated by the ESR of the output capacitors ...
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PWM comparator terminates the initial pulse. 8.6 V 0.45 V UVLO STARTUP NORMAL OPERATION t S Figure 4. Idealized Waveforms Normal Operation During normal operation, the duty cycle of the gate drivers remains approximately ...
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ESR and ESL of the bulk and high frequency decoupling capacitors, circuit traces, and vias; 4. output voltage ripple and noise. Budgeting the tolerance is left up to the designer who must take ...
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EMI. The minimum value of inductance which prevents inductor saturation or exceeding the rated FET current can be calculated as ...
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DV ESR + DI OUT ESR MAX Similarly, the maximum allowable ESL is calculated from the following formula: DV ESL ESL MAX + DI Selection of the Input Inductor A common requirement is that the buck controller must not disturb ...
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... FET junction−to−ambient thermal resistance. ΘJA Control IC Power Dissipation The power dissipation of the IC varies with the MOSFETs used and the CS5421 operating frequency. The CC average MOSFET gate charge current typically dominates the control IC power dissipation. R QJA ] The IC power dissipation is determined by the formula: ...
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... In applications where the internal slope compensation is insufficient, the performance of the CS5421−based regulator can be improved through the addition of a fixed amount of external slope compensation at the output of the PWM Error Amplifier (the COMP pin) during the regulator off− ...
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... When laying out the CPU buck regulator on a printed can circuit board, the following checklist should be used to CS ensure proper operation of the CS5421. 1. Rapid changes in voltage across parasitic capacitors and abrupt changes in current in parasitic inductors are major concerns for a good layout. ...
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... C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative CS5421 ...