ad1870arz-reel Analog Devices, Inc., ad1870arz-reel Datasheet - Page 13

• Manufacturer Part Number: ad1870arz-reel
• Description: Single-supply 16-bit Stereo Adc
• Manufacturer: Analog Devices, Inc.

REV. A
Timing Parameters
For master modes, a BCLK transmitting edge (labeled “XMIT”)
will be delayed from a CLKIN rising edge by t
in Figure 17. A LRCK transition will be delayed from a BCLK
transmitting edge by t
delayed from a BCLK transmitting edge by t
falling edge will be delayed from a BCLK transmitting edge by
t
transmitting edge of BCLK by t
For slave modes, an LRCK transition must be set up to a BCLK
sampling edge (labeled “SAMPLE”) by t
The DATA and TAG outputs will be delayed from an LRCK
transition by t
delayed from BCLK transmitting edge by t
Mode, Data Position Controlled by WCLK Input, WCLK must
be set up to a BCLK sampling edge by t
For both Master and Slave Modes, BCLK must have a mini-
mum LO pulsewidth of t
t
The AD1870 CLKIN and RESET timing is shown in Figure 19.
CLKIN must have a minimum LO pulsewidth of t
minimum HI pulsewidth of t
CLKIN is given by t
pulsewidth of t
requirements for RESET.
Master Clock (CLKIN) Considerations
It is recommended that the BCLK and LRCK are derived from
CLKIN to ensure correct phase relationships. The modulator
of the AD1870 runs at 64 × f
obtained when the BCLK rate equals 64 × f
BPWH
DLYBWF
.
. The DATA and TAG outputs will be delayed from a
DLYLRDT
RPWL
. Note that there are no setup or hold time
CLKIN
, and DATA and TAG outputs will be
DLYBLR
BPWL
. RESET must have a minimum LO
and a minimum HI pulsewidth of
. A WCLK rising edge will be
CPWH
S
. Therefore, best performance is
DLYDT
. The minimum period of
.
SETWBS
SETLRBS
DLYBWR
S
DLYBDT
or 32 × f
DLYCKB
.
(see Figure 18).
, and a WCLK
. For Slave
CPWL
, as shown
S
. BCLK
and a
–13–
rates such as 48 × f
floor, depending on the phase relationship of BCLK to CLKIN.
Synchronizing Multiple AD1870s
Multiple AD1870s can be synchronized by making all the
AD1870s serial port slaves. This option is illustrated in Figure 6.
See the Reset, Autocalibration, and Power-Down section for
additional information.
Figure 6. Synchronizing Multiple AD1870s
S
may result in an increased spectral noise
RESET
CLKIN
RESET
CLKIN
RESET
CLKIN
#1 AD1870
SLAVE MODE
#2 AD1870
SLAVE MODE
#N AD1870
SLAVE MODE
WCLK
WCLK
WCLK
DATA
BCLK
LRCK
DATA
BCLK
LRCK
DATA
BCLK
LRCK
SOURCE
CLOCK
AD1870