adc161s626cimmx National Semiconductor Corporation, adc161s626cimmx Datasheet - Page 17

• Manufacturer Part Number: adc161s626cimmx
• Description: 16-bit, 50 To 250 Ksps, Differential Input, Micropower Adc
• Manufacturer: National Semiconductor Corporation

Applications Information
OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC161S626:
−40°C
+4.5V
+2.7V
+0.5V
1 MHz
V
4.0 ANALOG INPUT CONSIDERATIONS
As stated previously in Section 2.6, it is not critical for the
performance of the ADC161S626 to filter out the voltage spike
that occurs when the ADC161S626 enters acquisition (t
mode at the end of the conversion window. However, it is crit-
ical that a system designer ensures that the transients of the
spike settle out within t
placed on the analog source itself or the burden can be shared
by the source and an external capacitor, C
Figure 15. The external capacitor acts as a local charge reser-
voir for the internal sampling capacitor and thus reduces the
size of the voltage spike. For low frequency analog sources
such as sensors with DC-like output behaviors, C
greater than 1 nF are recommended. However, some sensors
and signal conditioning circuitry will not be able to maintain
their stability in the presence of the external capacitive load.
In these instances, a series resistor (R
The magnitude of R
of the analog source and the settling requirement of the ADC.
Independent of the presence of an external capacitor, the
system designer always has the option of lowering the sample
rate of the ADC161S626 which directly controls the amount
of time allowed for the voltage spike to settle. The slower the
sample rate, the longer the t
possible with the ADC161S626 since the converter enters
t
analog input source the entire time between conversions.
5.0 POWER CONSUMPTION
The architecture, design, and fabrication process allow the
ADC161S626 to operate at conversion rates up to 250 kSPS
while consuming very little power. The ADC161S626 con-
sumes the least amount of power while operating in acquisi-
tion (power-down) mode. For applications where power
consumption is critical, the ADC161S626 should be operated
in acquisition mode as often as the application will tolerate.
To further reduce power consumption, stop the SCLK while
CS is high.
5.1 Short Cycling
Short cycling refers to the process of halting a conversion af-
ter the last needed bit is outputted. Short cycling can be used
to lower the power consumption in those applications that do
not need a full 16-bit resolution, or where an analog signal is
being monitored until some condition occurs. In some circum-
stances, the conversion could be terminated after the first few
bits. This will lower power consumption in the converter since
the ADC161S626 spends more time in acquisition mode and
less time in conversion mode.
Short cycling is accomplished by pulling CS high after the last
required bit is received from the ADC161S626 output. This is
possible because the ADC161S626 places the latest con-
verted data bit on D
conversion result are needed, for example, the conversion
ACQ
CM
: See Section 2.3
at the end of the prior conversion and thus is tracking the
≤
≤
≤
≤
≤
V
V
V
T
f
SCLK
A
IO
REF
A
≤
≤
≤
+5.5V
≤
+85°C
+5.5V
≤
+5.5V
5 MHz
OUT
EXT
as it is generated. If only 10-bits of the
ACQ
is dependent on the output capability
. The burden of this task can be
ACQ
time or settling time. This is
EXT
) is recommended.
EXT
as shown in
EXT
values
ACQ
)
17
can be terminated by pulling CS high after the 10
been clocked out.
5.2 Burst Mode Operation
Normal operation of the ADC161S626 requires the SCLK fre-
quency to be 20 times the sample rate and the CS rate to be
the same as the sample rate. However, in order to minimize
power consumption in applications requiring sample rates be-
low 250 kSPS, the ADC161S626 should be run with an SCLK
frequency of 5 MHz and a CS rate as slow as the system
requires. When this is accomplished, the ADC161S626 is op-
erating in burst mode. The ADC161S626 enters into acquisi-
tion mode at the end of each conversion, minimizing power
consumption. This causes the converter to spend the longest
possible time in acquisition mode. Since power consumption
scales directly with conversion rate, minimizing power con-
sumption requires determining the lowest conversion rate that
will satisfy the requirements of the system.
6.0 PCB LAYOUT AND CIRCUIT CONSIDERATIONS
For best performance, care should be taken with the physical
layout of the printed circuit board. This is especially true with
a low V
rates there is less time for settling, so it is important that any
noise settles out before the conversion begins.
6.1 Analog and Digital Power Supplies
Any ADC architecture is sensitive to spikes on the power sup-
ply, reference, and ground pins. These spikes may originate
from switching power supplies, digital logic, high power de-
vices, and other sources. Power to the ADC161S626 should
be clean and well bypassed. A 0.1 µF ceramic bypass ca-
pacitor and a 1 µF to 10 µF capacitor should be used to
bypass the ADC161S626 supply, with the 0.1 µF capacitor
placed as close to the ADC161S626 package as possible.
Since the ADC161S626 has both the V
has three options on how to connect these pins. The first op-
tion is to tie V
power supply. This is the most cost effective way of powering
the ADC161S626 but is also the least ideal. As stated previ-
ously, noise from V
performance. The other two options involve the user powering
V
ages can have the same amplitude or they can be different.
V
V
Best performance will typically be achieved with V
at 5V and V
and dynamic performance when V
operating V
digital logic. Operating the digital interface at 3V also has the
added benefit of decreasing the noise created by charging
and discharging the capacitance of the digital interface pins.
6.2 Voltage Reference
The reference source must have a low output impedance and
needs to be bypassed with a minimum capacitor value of 0.1
µF. A larger capacitor value of 1 µF to 10 µF placed in parallel
with the 0.1 µF is preferred. While the ADC161S626 draws
very little current from the reference on average, there are
higher instantaneous current spikes at the reference.
V
reject noise or voltage variations. Keep this in mind if V
derived from the power supply. Any noise and/or ripple from
the supply that is not rejected by the external reference cir-
cuitry will appear in the digital results. The use of an active
reference source is recommended. The LM4040 and LM4050
A
A
IO
REF
and V
can be set to any value between +4.5V and +5.5V; while
can be set to any value between +2.7V and +5.5V.
of the ADC161S626, like all A/D converters, does not
REF
IO
IO
or when the conversion rate is high. At high clock
with separate supply voltages. These supply volt-
IO
A
at 3V. Operating V
and V
at 3V reduces the power consumption of the
IO
IO
can couple into V
together and power them with the same
A
at 5V offers the best linearity
REF
A
is also set to 5V; while
A
and V
and adversely affect
IO
pins, the user
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A
operating
th
bit has
REF
is