adc161s626cimmx National Semiconductor Corporation, adc161s626cimmx Datasheet - Page 13

• Manufacturer Part Number: adc161s626cimmx
• Description: 16-bit, 50 To 250 Ksps, Differential Input, Micropower Adc
• Manufacturer: National Semiconductor Corporation

Functional Description
The ADC161S626 is a 16-bit, 50 kSPS to 250 kSPS sampling
Analog-to-Digital (A/D) converter. The converter uses a suc-
cessive approximation register (SAR) architecture based up-
on capacitive redistribution containing an inherent sample-
and-hold function. The differential nature of the analog inputs
is maintained from the internal sample-and-hold circuits
throughout the A/D converter to provide excellent common-
mode signal rejection.
The ADC161S626 operates from independent analog and
digital supplies. The analog supply (V
to 5.5V and the digital input/output supply (V
from 2.7V to 5.5V. The ADC161S626 utilizes an external ref-
erence (V
V
put, while the reference input current (I
conversion rate.
The analog input is presented to two input pins: +IN and –IN.
Upon initiation of a conversion, the differential input at these
pins is sampled on the internal capacitor array. The inputs are
disconnected from the internal circuitry while a conversion is
in progress. The ADC161S626 features a zero-power track
mode (ZPTM) where the ADC is consuming the minimum
amount of power (Power-Down Mode) while the internal sam-
pling capacitor array is tracking the applied analog input
voltage. The converter enters ZPTM at the end of each con-
version window and experiences no delay when the ADC
enters into Conversion Mode. This feature allows the user an
easy means for optimizing system performance based on the
settling capability of the analog source while minimizing pow-
er consumption. ZPTM is exercised by bringing chip select
bar (CS) high or when CS is held low after the conversion is
complete (after the 18
The ADC161S626 communicates with other devices via a
Serial Peripheral Interface (SPI™), a synchronous serial in-
terface that operates using three pins: chip select bar (CS),
serial clock (SCLK), and serial data out (D
SCLK controls data transfer and serves as the conversion
clock. The duty cycle of SCLK is essentially unimportant, pro-
vided the minimum clock high and low times are met. The
minimum SCLK frequency is set by internal capacitor leak-
age. Each conversion requires a minimum of 18 SCLK cycles
to complete. If less than 16 bits of conversion data are re-
quired, CS can be brought high at any point during the con-
version. This procedure of terminating a conversion prior to
completion is commonly referred to as short cycling.
The digital conversion result is clocked out by the SCLK input
and is provided serially, most significant bit (MSB) first, at the
D
that of the conversion currently in progress and thus there is
no pipe line delay or latency.
1.0 REFERENCE INPUT (V
The externally supplied reference voltage (V
analog input range. The ADC161S626 will operate with
V
Operation with V
minished performance. As V
acceptable analog input voltages is reduced. Assuming a
proper common-mode input voltage (V
A
REF
OUT
. The value of V
in the range of 0.5V to V
pin. The digital data that is provided at the D
REF
), which can be any voltage between 0.5V and
REF
REF
below 2.5V is possible with slightly di-
th
determines the range of the analog in-
falling edge of the serial clock).
REF
A
REF
.
)
is reduced, the range of
A
REF
) can range from 4.5V
CM
) depends upon the
OUT
), the differential
). The external
IO
REF
) can range
) sets the
OUT
pin is
13
peak-to-peak input range is limited to (2 x V
2.3 for more details.
Reducing V
bit (LSB). For example, the size of one LSB is equal to [(2 x
V
5V. When the LSB size goes below the noise floor of the
ADC161S626, the noise will span an increasing number of
codes and overall performance will suffer. Dynamic signals
will have their SNR degrade; while, D.C. measurements will
have their code uncertainty increase. Since the noise is Gaus-
sian in nature, the effects of this noise can be reduced by
averaging the results of a number of consecutive conver-
sions.
V
capacitor array through a switch matrix when the input is
sampled. Hence, I
spikes that occur at a frequency dependent on the operating
sample rate of the ADC161S626.
I
“Reference Current vs. SCLK Frequency” and “Reference
Current vs. Temperature” in the Typical Performance Curves
section for additional details.
2.0 ANALOG SIGNAL INPUTS
The ADC161S626 has a differential input where the effective
input voltage that is digitized is (+IN) − (−IN).
2.1 Differential Input Operation
The transfer curve of the ADC161S626 for a fully differential
input signal is shown in Figure 7. A positive full scale output
code (0111 1111 1111 1111b or 7FFFh or 32,767d) will be
obtained when (+IN) − (−IN) is greater than or equal to
(V
0000b or 8000h or -32,768d) will be obtained when [(+IN) −
(−IN)] is less than or equal to (−V
gain, offset and linearity errors, which will affect the exact dif-
ferential input voltage that will determine any given output
code.
REF
REF
REF
REF
changes only slightly with temperature. See the curves,
) / 2
and analog inputs (+IN and -IN) are connected to the
− 1 LSB). A negative full scale code (1000 0000 0000
n
], which is 152.6 µV where n is 16 bits and V
REF
FIGURE 7. ADC Transfer Curve
also reduces the size of the least significant
REF
, I
+IN
, and I
-IN
REF
are a series of transient
+ 1 LSB). This ignores
REF
). See Section
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30073499
REF
is